Memory module with a circuit providing load isolation and memory domain translation

• US 7,636,274 B2
• Filed: 03/20/2009
• Issued: 12/22/2009
• Est. Priority Date: 03/05/2004
• Status: Expired due to Fees

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Solomon, Jeffrey C, Bhakta, Jayesh R
• Primary Examiner(s): Nguyen; Tuan T
• Assistant Examiner(s): Sofocleous; Alexander
• Application Number:
  US12/408,652
• Publication Number:
  US 20090201711A1
• Time in Patent Office: 277 Days
• Field of Search: 365/51, 365/52, 365/230.01, 365/230.02, 365/230.06, 365/233.1, 365/233.13, 365/189.02, 365/230.03, 711/105, 711/154
• US Class Current: 365/233.13
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/10159 Memory
• CPC Class Codes: H05K 2203/1572 Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one or more of the loads of the memory devices from the computer system. The circuit comprises logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module.

Claims

1. A memory module comprising:

a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks, each DDR memory device having a corresponding load;

a circuit comprising a logic element and a register, the circuit electrically coupled to the plurality of DDR memory devices and configured to be electrically coupled to a memory controller of a computer system to receive a set of input signals from the computer system, the set of input signals comprising row/column address signals, bank address signals, and chip-select signals, the set of input signals compatible with a system memory domain of the computer system, the circuit configurable to be responsive to the set of input signals by selectively isolating one or more of the loads of the DDR memory devices from the computer system, the circuit configurable to translate between the system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain has a first memory density per rank, and the physical memory domain has a second memory density per rank less than the first memory density per rank; and

a phase-lock loop device operationally coupled to the plurality of DDR memory devices, the logic element, and the register.

2. The memory module of claim 1, wherein the logic element is selected from a group consisting of:

a programmable-logic device, an application-specific integrated circuit, a field-programmable gate array, a custom-designed semiconductor device, and a complex programmable-logic device.

3. The memory module of claim 2, wherein the circuit further comprises one or more switches operatively coupled to the logic element to receive control signals from the logic element.

4. The memory module of claim 1, wherein the plurality of DDR memory devices has a first number of DDR memory devices, and the circuit is configurable to selectively isolate the loads of a second number of the DDR memory devices from the computer system, the second number less than the first number.

5. The memory module of claim 4, wherein the first number of DDR memory devices are configured in a plurality of ranks, and wherein the second number of DDR memory devices are configured as one rank of the plurality of ranks.

6. The memory module of claim 1, wherein the circuit is configurable to translate address signals in the system memory domain to address signals in the physical memory domain.

7. The memory module of claim 1, wherein the system memory domain is compatible with a first number of chip selects, and the physical memory domain is compatible with a second number of chip selects equal to twice the first number of chip selects.

8. The memory module of claim 1, wherein the first memory density per rank is equal to twice the second memory density per rank.

9. The memory module of claim 1, wherein the plurality of DDR memory devices are arranged in two or more ranks of memory devices.

10. The memory module of claim 9, wherein the circuit comprises a data path multiplexer/demultiplexer which isolates the ranks of DDR memory devices from one another.

11. The memory module of claim 1, wherein the plurality of DDR memory devices comprises a pair of DDR memory devices, each DDR memory device of the pair having a first memory capacity, the pair of DDR memory devices configured to simulate a DDR memory device having a second memory capacity greater than the first memory capacity.

12. The memory module of claim 11, wherein the second memory capacity is twice the first memory capacity.

13. The memory module of claim 1, wherein two or more of the phase-lock loop device, the logic element, and the register are portions of a single component.

14. The memory module of claim 1, wherein the memory module comprises a registered dual inline memory module.

15. The memory module of claim 14, wherein the plurality of DDR memory devices comprises DDR3 synchronous dynamic random-access memory (SDRAM) devices.

16. The memory module of claim 1, wherein the circuit is configurable to selectively isolate the loads of the DDR memory devices from the computer system in response to a command or address signal of the set of input signals.

17. The memory module of claim 1, further comprising a printed circuit board configured to be electrically coupled to the memory controller, the circuit mounted on the printed circuit board, the plurality of DDR memory devices mounted on the printed circuit board as a first set of DDR memory devices on a first side of the printed circuit board, a second set of DDR memory devices on the first side of the printed circuit board, a third set of DDR memory devices on a second side of the printed circuit board, and a fourth set of DDR memory devices on the second side of the printed circuit board, the DDR memory devices of the second set spaced from the DDR memory devices of the first set, the DDR memory devices of the fourth set spaced from the DDR memory devices of the third set.

18. The memory module of claim 1, wherein the circuit is configurable to transmit a set of output signals to the plurality of DDR memory devices, the set of output signals compatible with the physical memory domain.

19. The memory module of claim 18, wherein the set of input signals comprises a command signal and the set of output signals comprises the command signal.

20. The memory module of claim 18, wherein the circuit is configurable to receive a command signal from the computer system, select at least one rank of the one or more ranks, and transmit the command signal to at least one DDR memory device of the selected rank of DDR memory devices.

21. The memory module of claim 18, wherein the set of input signals comprises a first set of address and command signals and the set of output signals comprises a second set of address and command signals.

22. The memory module of claim 21, wherein the circuit is configurable to store an address signal of the set of input signals during a row access procedure and pass the stored address signal as an address signal of the set of output signals during a subsequent column address procedure.

23. The memory module of claim 1, wherein the circuit is configurable to selectively isolate a data signal line of a DDR memory device of the plurality of DDR memory devices from the computer system.

24. The memory module of claim 1, wherein the circuit is configurable to receive a row/column address signal of the set of input signals and to use the row/column address signal to translate between the system memory domain and the physical memory domain.

25. The memory module of claim 24, wherein the row/column address signal is a row address bit and the circuit is configurable to latch the row address bit.

26. The memory module of claim 24, wherein the row/column address signal is a row address bit and the circuit is configurable to use the row address bit and a first number of chip-select signals of the set of input signals to generate a second number of chip-select signals greater than the first number of chip-select signals.

27. The memory module of claim 24, wherein the row/column address signal is a row address bit and the circuit is configurable to use the row address bit and a first number of column address strobe (CAS) signals to generate a second number of CAS signals greater than the first number of CAS signals.

28. A method of using a memory module with a computer system, the method comprising:

providing a memory module having a plurality of dual-data-rate (DDR) memory devices arranged in one or more ranks and a circuit electrically coupled to the plurality of DDR memory devices, the circuit comprising a logic element, a register, and a phase-lock loop device, the phase-lock loop device operatively coupled to the plurality of DDR memory devices, the logic element, and the register, the circuit configured to be electrically coupled to a computer system to receive a set of input signals from the computer system, the set of input signals comprising row/column address signals, bank address signals, and chip-select signals, the set of input signals compatible with a system memory domain of the computer system, each DDR memory device having a corresponding load;

electrically coupling the memory module to the computer system; and

activating the circuit in response to the set of input signals to selectively isolate at least one of the loads of the DDR memory devices from the computer system and to translate between the system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain has a first memory density per rank, and the physical memory domain has a second memory density per rank less than the first memory density per rank.

29. The method of claim 28, wherein the plurality of DDR memory devices comprises a first number of DDR memory devices and activating the circuit selectively isolates the loads of a second number of DDR memory devices from the computer system, the second number less than the first number.

30. The method of claim 29, wherein the first number of DDR memory devices are arranged in two or more ranks of DDR memory devices, and wherein the second number of DDR memory devices are arranged as one rank of the two or more ranks.

31. The method of claim 28, further comprising storing an address signal of the set of input signals during a row access procedure and passing the stored address signal as an address signal of a set of output signals during a subsequent column address procedure.

32. The method of claim 28, wherein the plurality of DDR memory devices comprises a pair of DDR memory devices, each DDR memory device of the pair having a first memory capacity, the pair of DDR memory devices configured to simulate a DDR memory device having a second memory capacity equal to twice the first memory capacity.

33. The method of claim 28, wherein two or more of the logic element, the register, and the phase-lock loop device are portions of a single component.

34. The method of claim 28, wherein upon said activation, the circuit is responsive to the set of input signals to selectively isolate a data signal line of a DDR memory device of the plurality of DDR memory devices from the computer system.

35. The method of claim 28, wherein upon said activation, the circuit uses a row/column address signal of the set of input signals to translate between the system memory domain and the physical memory domain.

36. The method of claim 35, wherein the row/column address signal is a row address bit and the circuit latches the row address bit.

37. The method of claim 35, wherein the row/column address signal is a row address bit and the circuit uses the row address bit and a first number of chip-select signals of the set of input signals to generate a second number of chip-select signals greater than the first number of chip-select signals.

38. The method of claim 35, wherein the row/column address signal is a row address bit and the circuit uses the row address bit and a first number of column address strobe (CAS) signals to generate a second number of CAS signals greater than the first number of CAS signals.

39. A memory module connectable to a computer system, the memory module comprising:

a first dual-data-rate (DDR) memory device having a first data signal line and a first data strobe signal line;

a second DDR memory device having a second data signal line and a second data strobe signal line;

a common data signal line connectable to the computer system; and

a circuit comprising a logic element, a register, and a phase-lock loop device operationally coupled to the first DDR memory device, the second DDR memory device, the logic element, and the register, the circuit configured to be electrically coupled to a memory controller of a computer system to receive a set of input signals from the computer system, the set of input signals comprising row address signals, column address signals, bank address signals, and chip-select signals, the set of input signals compatible with a system memory domain of the computer system, the circuit electrically coupled to the first data signal line, to the second data signal line, and to the common data signal line, the circuit configurable to be responsive to the set of input signals by selectively electrically coupling the first data signal line to the common data signal line and selectively electrically coupling the second data signal line to the common data signal line, the circuit configurable to translate between the system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain has a first memory density per memory device, and the physical memory domain has a second memory density per memory device less than the first memory density per memory device.

40. The memory module of claim 39, wherein the two or more of the logic element, the register, and the phase-lock loop device are portions of a single component.

41. The memory module of claim 40, wherein the circuit further comprises one or more switches selectively electrically coupling the first data signal line to the common data signal line and selectively electrically coupling the second data signal line to the common data signal line, the one or more switches operatively coupled to the logic element to receive control signals from the logic element.

42. The memory module of claim 39, wherein the logic element is selected from the group consisting of:

an application-specific integrated circuit, a custom-programmable logic device, and a field-programmable gate array.

43. The memory module of claim 39, wherein the register comprises a plurality of register devices.

44. The memory module of claim 39, wherein the circuit is configurable to translate address signals in the system memory domain to address signals in the physical memory domain.

45. The memory module of claim 39, wherein the system memory domain is compatible with a first number of chip select signals, and the physical memory domain is compatible with a second number of chip select signals greater than the first number of chip select signals.

46. The memory module of claim 45, wherein the second number of chip select signals is equal to twice the first number of chip select signals.

47. The memory module of claim 39, wherein the memory module further comprises a third data strobe signal line connectable to the computer system, the circuit electrically coupled to the first data strobe signal line, to the second data strobe signal line, and to the third data strobe signal line, the circuit selectively electrically coupling the first data strobe signal line to the third data strobe signal line and selectively electrically coupling the second data strobe signal line to the third data strobe signal line.

48. The memory module of claim 39, wherein the circuit is configurable to transmit a set of output signals to at least one of the first and second DDR memory devices, the set of output signals compatible with the physical memory domain.

49. The memory module of claim 48, wherein the set of input signals comprises a command signal and the set of output signals comprises the command signal.

50. The memory module of claim 48, wherein the circuit is configurable to receive a command signal from the computer system and transmit the command signal to the at least one of the first and second DDR memory devices.

51. The memory module of claim 48, wherein the set of output signals comprises row address signals, column address signals, bank address signals, and chip-select signals.

52. The memory module of claim 48, wherein the set of input signals comprises a first set of address and command signals and the set of output signals comprises a second set of address and command signals.

53. The memory module of claim 52, wherein the circuit is configurable to save an address signal of the set of input signals during a row access procedure and pass the saved address signal as an address signal of the set of output signals during a subsequent column address procedure.

54. The memory module of claim 39, wherein the circuit is configurable to be responsive to the set of input signals by selectively electrically coupling both the first data signal line and the second data signal line to the computer system.

55. The memory module of claim 39, wherein the circuit is configurable to selectively isolate both the first data signal line and the second data signal line from the computer system.

56. A memory module comprising:

a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks, each DDR memory device having a corresponding load; and

a circuit comprising a logic element, a register, and a phase-lock loop device operationally coupled to the plurality of DDR memory devices, the logic element, and the register, the circuit electrically coupled to the plurality of DDR memory devices and configured to be electrically coupled to a memory controller of a computer system to receive a set of input signals from the computer system, the set of input signals comprising row/column address signals, bank address signals, and chip-select signals, the set of input signals compatible with a system memory domain of the computer system, the circuit configurable to be responsive to the set of input signals by selectively isolating one or more of the loads of the DDR memory devices from the computer system, the circuit configurable to translate between the system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain is compatible with a first number of chip-select signals, and the physical memory domain is compatible with a second number of chip-select signals greater than the first number of chip-select signals.

57. The memory module of claim 56, wherein the circuit comprises one or more switches operatively coupled to the logic element to receive control signals from the logic element.

58. The memory module of claim 56, wherein the plurality of DDR memory devices has a first number of DDR memory devices, and the circuit is configurable to selectively isolate the loads of a second number of the DDR memory devices from the computer system, the second number less than the first number.

59. The memory module of claim 58, wherein the first number of DDR memory devices are configured in a plurality of ranks, and wherein the second number of DDR memory devices are configured as one rank of the plurality of ranks.

60. The memory module of claim 56, wherein the second number of chip-select signals is equal to twice the first number of chip-select signals.

61. The memory module of claim 56, wherein the circuit comprises a data path multiplexer/demultiplexer which isolates the ranks of DDR memory devices from one another.

62. The memory module of claim 56, wherein the plurality of DDR memory devices comprises a pair of DDR memory devices, each DDR memory device of the pair having a first memory capacity, the pair of DDR memory devices configured to simulate a DDR memory device having a second memory capacity greater than the first memory capacity.

63. The memory module of claim 56, wherein two or more of the logic element, the register, and the phase-lock loop device are portions of a single component.

64. The memory module of claim 56, wherein the memory module comprises a registered dual inline memory module.

65. The memory module of claim 56, wherein the plurality of DDR memory devices comprises DDR3 synchronous dynamic random-access memory (SDRAM) devices.

66. The memory module of claim 56, further comprising a printed circuit board configured to be electrically coupled to the memory controller, the circuit mounted on the printed circuit board, the plurality of DDR memory devices mounted on the printed circuit board as a first set of DDR memory devices on a first side of the printed circuit board, a second set of DDR memory devices on the first side of the printed circuit board, a third set of DDR memory devices on a second side of the printed circuit board, and a fourth set of DDR memory devices on the second side of the printed circuit board, the DDR memory devices of the second set spaced from the DDR memory devices of the first set, the DDR memory devices of the fourth set spaced from the DDR memory devices of the third set.

67. The memory module of claim 56, wherein the circuit is configurable to receive a command signal from the computer system, select at least one rank of the one or more ranks, and transmit the command signal to at least one DDR memory device of the selected rank of DDR memory devices.

68. The memory module of claim 56, wherein the set of input signals comprises a first set of address and command signals and the set of output signals comprises a second set of address and command signals, wherein the circuit is configurable to store an address signal of the set of input signals during a row access procedure and pass the stored address signal as an address signal of the set of output signals during a subsequent column address procedure.

69. The memory module of claim 56, wherein the circuit is configurable to selectively isolate a data signal line of a DDR memory device of the plurality of DDR memory devices from the computer system.

70. The memory module of claim 56, wherein the circuit is configurable to receive a row/column address signal of the set of input signals and to use the row/column address signal to translate between the system memory domain and the physical memory domain.

71. The memory module of claim 70, wherein the row/column address signal is a row address bit and the circuit is configurable to latch the row address bit.

72. The memory module of claim 70, wherein the row/column address signal is a row address bit and the circuit is configurable to use the row address bit and a first number of chip-select signals of the set of input signals to generate a second number of chip-select signals greater than the first number of chip-select signals.

73. The memory module of claim 70, wherein the row/column address signal is a row address bit and the circuit is configurable to use the row address bit and a first number of column address strobe (CAS) signals to generate a second number of CAS signals greater than the first number of CAS signals.

79. The method of claim 70, wherein upon said activation, the circuit is responsive to the set of input signals to selectively isolate a data signal line of a DDR memory device of the plurality of DDR memory devices from the computer system.

74. A method of using a memory module with a computer system, the method comprising:

providing a memory module having a plurality of dual-data-rate (DDR) memory devices arranged in one or more ranks and a circuit electrically coupled to the plurality of DDR memory devices, the circuit comprising a logic element, a register, and a phase-lock loop device operationally coupled to the plurality of DDR memory devices, the logic element, and the register, the circuit configured to be electrically coupled to a computer system to receive a set of input signals from the computer system, the set of input signals comprising row/column address signals, bank address signals, and chip-select signals, the set of input signals compatible with a system memory domain of the computer system, each DDR memory device having a corresponding load;

electrically coupling the memory module to the computer system; and

activating the circuit in response to the set of input signals to selectively isolate at least one of the loads of the DDR memory devices from the computer system and to translate between the system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain is compatible with a first number of chip-select signals, and the physical memory domain is compatible with a second number of chip-select signals greater than the first number of chip-select signals.

75. The method of claim 74, wherein the plurality of DDR memory devices comprises a first number of DDR memory devices and activating the circuit selectively isolates the loads of a second number of DDR memory devices from the computer system, the second number less than the first number.

76. The method of claim 75, wherein the first number of DDR memory devices are arranged in two or more ranks of DDR memory devices, and wherein the second number of DDR memory devices are arranged as one rank of the two or more ranks.

77. The method of claim 74, further comprising storing an address signal of the set of input signals during a row access procedure and passing the stored address signal as an address signal of a set of output signals during a subsequent column address procedure.

78. The method of claim 74, wherein two or more of the logic element, the register, and the phase-lock loop device are portions of a single component.

80. The method of claim 74, wherein upon said activation, the circuit uses a row/column address signal of the set of input signals to translate between the system memory domain and the physical memory domain.

81. The method of claim 80, wherein the row/column address signal is a row address bit and the circuit latches the row address bit.

82. The method of claim 80, wherein the row/column address signal is a row address bit and the circuit uses the row address bit and a first number of chip-select signals of the set of input signals to generate a second number of chip-select signals greater than the first number of chip-select signals.

83. The method of claim 80, wherein the row/column address signal is a row address bit and the circuit uses the row address bit and a first number of column address strobe (CAS) signals to generate a second number of CAS signals greater than the first number of CAS signals.

84. A memory module connectable to a computer system, the memory module comprising:

a first dual-data-rate (DDR) memory device having a first data signal line and a first data strobe signal line;

a second DDR memory device having a second data signal line and a second data strobe signal line;

a common data signal line connectable to the computer system; and

a circuit comprising a logic element, a register, and a phase-lock loop device operationally coupled to the first DDR memory device, the second DDR memory device, the logic element, and the register, the circuit configured to be electrically coupled to a memory controller of a computer system to receive a set of input signals from the computer system, the set of input signals comprising row/column address signals, bank address signals, and a first number of chip-select signals, the set of input signals compatible with a system memory domain of the computer system, the circuit electrically coupled to the first data signal line, to the second data signal line, and to the common data signal line, the circuit configurable to be responsive to the set of input signals by selectively electrically coupling the first data signal line to the common data signal line and selectively electrically coupling the second data signal line to the common data signal line, the circuit configurable to translate between the system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain is compatible with the first number of chip-select signals, and the physical memory domain is compatible with a second number of chip-select signals greater than the first number of chip-select signals.

85. The memory module of claim 84, wherein two or more of the logic element, the register, and the phase-lock loop device are portions of a single component.

86. The memory module of claim 84, wherein the circuit further comprises one or more switches selectively electrically coupling the first data signal line to the common data signal line and selectively electrically coupling the second data signal line to the common data signal line, the one or more switches operatively coupled to the logic element to receive control signals from the logic element.

87. The memory module of claim 84, wherein the logic element comprises an application-specific integrated circuit, a field-programmable gate array, or a programmable-logic device.

88. The memory module of claim 84, wherein the second number of chip-select signals is equal to twice the first number of chip-select signals.

89. The memory module of claim 84, wherein the memory module further comprises a third data strobe signal line connectable to the computer system, the circuit electrically coupled to the first data strobe signal line, to the second data strobe signal line, and to the third data strobe signal line, the circuit selectively electrically coupling the first data strobe signal line to the third data strobe signal line and selectively electrically coupling the second data strobe signal line to the third data strobe signal line.

90. The memory module of claim 84, wherein the circuit is configurable to transmit a set of output signals to at least one of the first and second DDR memory devices, the set of output signals comprising row/column address signals, bank address signals, and the second number chip-select signals, the set of output signals compatible with the physical memory domain.

91. The memory module of claim 90, wherein the set of input signals comprises a command signal and the set of output signals comprises the command signal.

92. The memory module of claim 90, wherein the circuit is configurable to receive a command signal from the computer system and transmit the command signal to the at least one of the first and second DDR memory devices.

93. The memory module of claim 90, wherein the circuit is configurable to save an address signal of the set of input signals during a row access procedure and pass the saved address signal as an address signal of the set of output signals during a subsequent column address procedure.

94. The memory module of claim 84, wherein the circuit is configurable to be responsive to the set of input signals by selectively electrically coupling both the first data signal line and the second data signal line to the computer system.

95. The memory module of claim 84, wherein the circuit is configurable to selectively isolate both the first data signal line and the second data signal line from the computer system.

96. A circuit configured to be mounted on a memory module so as to be electrically coupled to a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks on the memory module, the memory module configured to be electrically coupled to a memory controller of a computer system so as to receive a set of input signals from the computer system, the set of input signals comprising row/column address signals, bank address signals, and chip-select signals, the set of input signals compatible with a system memory domain of the computer system, the circuit comprising:

a logic element;

a register;

a phase-lock loop device configured to be operationally coupled to the plurality of DDR memory devices, the logic element and the register,

wherein the circuit is configurable to be responsive to the set of input signals by selectively isolating one or more loads of the DDR memory devices from the computer system, the circuit configurable to translate between the system memory domain of the computer system and a physical memory domain of the plurality of DDR memory devices, wherein the system memory domain has a first memory density per rank and the physical memory domain has a second memory density per rank less than the first memory density per rank.

97. The circuit of claim 96, wherein two or more of the phase-lock loop device, the logic element, and the register are portions of a single component.