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System and method for high speed packet transmission implementing dual transmit and receive pipelines

  • US 7,636,369 B2
  • Filed: 11/29/2004
  • Issued: 12/22/2009
  • Est. Priority Date: 05/15/2003
  • Status: Active Grant
First Claim
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1. An integrated circuit having a plurality of ports, the integrated circuit comprising:

  • a plurality of cores each operative to provide a receive and transmit pipeline for packets corresponding to a given one of the ports, the plurality of cores each comprisinga local switching circuit operative to transfer packets between a first of the cores and a second of the cores.

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