System and method for high speed packet transmission implementing dual transmit and receive pipelines

• US 7,636,369 B2
• Filed: 11/29/2004
• Issued: 12/22/2009
• Est. Priority Date: 05/15/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Foundry Networks Incorporated (Broadcom, Inc.)
• Inventors: Wong, Yuen Fai
• Primary Examiner(s): PHAM, BRENDA H
• Application Number:
  US11/000,359
• Publication Number:
  US 20050175018A1
• Time in Patent Office: 1,849 Days
• Field of Search: 370/359, 370/358, 370/362, 370/364, 370/366, 370/389, 370/401, 370/402, 370/428, 370/419, 370/412, 370/462, 370/360, 370/386, 370/388, 370/396, 370/420, 370/421
• US Class Current: 370/419
• CPC Class Codes: H04L 12/4645 Details on frame tagging routing of packets H04L45/00; support for virtual LAN H04L49/354
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 45/7453 using hashing
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3063 Pipelined operation
• CPC Class Codes: H04L 49/352 Gigabit ethernet switching [GBPS]
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04Q 11/0428 Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals

Abstract

The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

Claims

1. An integrated circuit having a plurality of ports, the integrated circuit comprising:

a plurality of cores each operative to provide a receive and transmit pipeline for packets corresponding to a given one of the ports, the plurality of cores each comprising

a local switching circuit operative to transfer packets between a first of the cores and a second of the cores.

2. The integrated circuit of claim 1 wherein each core in the plurality of cores comprises a transmit quality of service module operative to determine the order in which packets received at the core from the backplane and the local switching circuit are transmitted to a memory structure.

3. The integrated circuit of claim 1 comprising a backplane transmit sorter circuit operative to organize packets for dispatch to one or more slots on a backplane of a switching or routing device.

4. The integrated circuit of claim 3 wherein the backplane transmit sorter circuit implements a number of FIFOs to organize packets prior to transmission to the one or more slots on the backplane.

5. The integrated circuit of claim 4 wherein the backplane transmit sorter circuit implements a number of FIFOs equal to a number of slots on the backplane.

6. The integrated circuit of claim 1 comprising a receive FIFO arbiter circuit, coupled between the cores and the backplane, operative to arbitrate the receipt of data from a plurality of transmit cores for placement in one or more receive FIFOs.

7. The integrated circuit of claim 1 comprising a backplane transmit grouper circuit, coupled between the cores and the backplane, operative to modify the size of a packet for transmission over the backplane.

8. The integrated circuit of claim 1, wherein the local switching circuit comprises a FIFO.

9. An integrated circuit having a plurality of ports, the integrated circuit comprising:

a first core; and

a second core;

wherein the first core is configured to provide

a first pipeline for processing packets received via a first port from the plurality of ports,

a second pipeline for processing packets to be transmitted via the first port, and

a first local switching circuit configured to enable packets to be passed between the first core and the second core;

wherein the second core is configured to provide

a first pipeline for processing packets received via a second port from the plurality of ports,

a second pipeline for processing packets to be transmitted via the second port, and

a second local switching circuit configured to enable packets to be passed between the first core and the second core.

10. An integrated circuit comprising:

a first core; and

a second core;

wherein the first core comprises a first local switching circuit to enable packets to be passed between the first core and the second core; and

wherein the second core comprises a second local switching circuit to enable packets to be passed between the first core and the second core.

11. The integrated circuit of claim 10 wherein the first local switching circuit comprises a FIFO.

12. The integrated circuit of claim 10 wherein the first local switching circuit comprises a FIFO and the second local switching circuit comprises a FIFO.

13. The integrated circuit of claim 10 wherein the first core comprises a transmit quality of service module operative to determine the order in which packets received at the first core from the second local switching circuit are transmitted.

14. The integrated circuit of claim 10 wherein the first local switching circuit and the second local switching circuit comprise a data pathway for switching packets between the first core and the second core without having to route the packets over a backplane.

15. An integrated circuit comprising:

a first core configured to receive and transmit packets;

the second core configured to receive and transmit packets;

wherein the first core comprises a first local switching circuit to enable the received packets to be passed between the first core and the second core; and

wherein the second core comprises a second local switching circuit to enable the received packets to be passed between the first core and the second core.

16. The integrated circuit of claim 15 wherein the first local switching circuit comprises a FIFO.

17. The integrated circuit of claim 15 wherein the first local switching circuit comprises a FIFO and the second local switching circuit comprises a FIFO.

18. The integrated circuit of claim 15 wherein the first core comprises a transmit quality of service module operative to determine the order in which packets received at the first core from the second local switching circuit are transmitted.

19. The integrated circuit of claim 15 wherein the first local switching circuit and the second local switching circuit comprise a data pathway for switching packets between the first core and the second core without having to route the packets over a backplane.