Multiplex bus system with duty cycle correction

• US 7,636,410 B2
• Filed: 02/07/2003
• Issued: 12/22/2009
• Est. Priority Date: 02/11/2002
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Vandensande, Geert Maria Marcel
• Primary Examiner(s): Fan; Chieh M.
• Assistant Examiner(s): Aghdam; Freshteh N
• Application Number:
  US10/360,436
• Publication Number:
  US 20030154418A1
• Time in Patent Office: 2,510 Days
• Field of Search: 375/355, 375/377, 375/354, 327/172, 327/175
• US Class Current: 375/355
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: H04L 12/04 Switchboards
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

The present invention is related to a method for treating a digital signal within a protocol handler which is part of a module coupled to a multiplex bus. The method consists in detecting the duty cycle of the digital signal, and in modifying said digital signal so that the modified signal contains the same data, but has a duty cycle of approximately 50%.

Claims

1. Method for correcting the duty cycle of a received signal, wherein said signal comprises a synchronization field (22), said synchronization field comprising a number of cycles of a high state followed by a low state or vice versa, said method comprising the steps of:

transforming said signal into a first block wave (30;

21 to 24), representing a sequence of high and low states, a high state corresponding to a first binary value, a low state corresponding to a second binary value,

oversampling said first block wave with a sample signal (35) having a sample period equal to Δ

t,

deriving from at least a part of said first block wave, the duty cycle of said first block wave by counting the number of samples, obtained by oversampling and corresponding to a high state and the number of samples, obtained by oversampling and corresponding to a low state in one or more cycles of the incoming signal and,

producing a second block wave (44), which represents the same sequence of high and low states as said first block wave, and wherein at least a part of said second block wave has a duty cycle of 50%,

after oversampling said first block wave (30;

21 to 24) with said sample signal (35), deriving the number of samples (n), obtained by oversampling and corresponding to a predefined number of high states of said synchronization field (22) and the number of samples (m), obtained by oversampling and corresponding to a predefined number of low states of said synchronization field (22), wherein said predefined number is called ‘

x’

,

calculating from said numbers n and m, the duty cycle of said first block wave (22),

if n<

m, delaying each high to low transition relative to the previous low to high transition in at least a part of said first block wave (30;

21 to 24), with a time equal to (m−

n/2x), At, thereby producing said second block wave (44),

if n>

m, delaying each low to high transition relative to the previous high to low transition in at least a part of said first block wave (30;

21 to 24), with a time equal to (n−

m/2x), Δ

t, thereby producing said second block wave (44).