Flash memory cell arrays having dual control gates per memory cell charge storage element

• US 7,638,834 B2
• Filed: 06/02/2006
• Issued: 12/29/2009
• Est. Priority Date: 10/28/2002
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou
• Primary Examiner(s): Tran; Thien F
• Application Number:
  US11/422,016
• Publication Number:
  US 20060202256A1
• Time in Patent Office: 1,306 Days
• Field of Search: 257/319, 257/320
• US Class Current: 257/319
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.

Claims

1. A non-volatile memory cell array comprising a plurality of strings of series connected memory cells extending in a first direction across a semiconductor substrate, the memory cells including charge storage elements, the array including control lines extending in a second direction across the strings of memory cells and including control gates adjacent charge storage elements thereof, the first and second directions being orthogonal with each other, wherein the control gates are positioned between adjacent charge storage elements of the memory strings in a manner to individually be capacitively coupled with sidewalls of the adjacent charge storage elements of the memory cell strings on opposite sides of the control gates, and wherein opposing sidewalls of individual charge storage elements are capacitively coupled with a pair of the plurality of control gate lines located on either side thereof.

2. The memory cell array of claim 1, wherein the control lines are additionally capacitively coupled with regions of the substrate between the charge storage elements.

4. The memory cell array of either of claims 2 or 3, wherein the capacitive coupling of the control lines with the substrate regions is characterized by enhancing the conductivity of the substrate regions in response to voltages placed on the control lines.

3. A non-volatile memory cell array comprising a plurality of strings of series connected memory cells extending in a first direction across a semiconductor substrate, the memory cells including charge storage elements, the array including control lines extending in a second direction across the strings of memory cells and including control gates adjacent charge storage elements thereof, the first and second directions being orthogonal with each other, wherein the control gates are positioned between adjacent charge storage elements of the memory strings in a manner to individually be capacitively coupled with sidewalls of the adjacent charge storage elements of the memory cell strings on opposite sides of the control gates, and wherein opposing sidewalls of individual charge storage elements are capacitively coupled with a pair of the plurality of control gate lines located on either side thereof, and further wherein the control lines are additionally capacitively coupled with regions of the substrate between the charge storage elements and extend into trenches formed in the substrate regions with a layer of dielectric therebetween.

5. A non-volatile memory cell array comprising a plurality of strings of series connected memory cells extending in a first direction across a semiconductor substrate, the memory cells including charge storage elements, the array including control lines extending in a second direction across the strings of memory cells and including control gates adjacent charge storage elements thereof, the first and second directions being orthogonal with each other, wherein the control gates are positioned between adjacent charge storage elements of the memory strings in a manner to individually be capacitively coupled with sidewalls of the adjacent charge storage elements of the memory cell strings on opposite sides of the control gates, and wherein opposing sidewalls of individual charge storage elements are capacitively coupled with a pair of the plurality of control gate lines located on either side thereof, and further wherein the charge storage elements include conductive floating gates that individually have heights extending above the substrate a distance that is larger than their widths, and wherein the control lines extend above the substrate at least as far as the heights of the floating gates to which the control gates are capacitively coupled.

6. The memory cell array of claim 5, wherein a bottom portion of the control lines includes a doped polysilicon material and a top portion of the control lines includes a metal or silicide material in contact with the doped polysilicon material.

7. The memory cell array of claim 6, wherein each of said control lines is positioned within the spacing between adjacent ones of the floating gates in order to be electrically isolated from one another.

8. A non-volatile memory system, comprising:

(a) a memory cell array, including;

a plurality of strings of series connected memory cells extending in a first direction across a semiconductor substrate and being spaced apart in a second direction, the first and second directions being perpendicular, the memory cells individually including a charge storage element and ends of the strings of series connected memory cells being connected with a plurality of bit lines, and

control gate lines extending in a second direction across multiple strings of memory cells and being positioned in the first direction between adjacent charge storage elements, wherein opposing sidewalls of individual charge storage elements are capacitively coupled with both of the control gates on opposite sides thereof, and

(b) a voltage supply circuit connected to the control gate and bit lines that simultaneously provides operating voltages, including;

first voltages to a pair of control gate lines on opposite sides of at least a first row of charge storage elements across the plurality of strings in order to raise voltage levels of at least the first row of charge storage elements to levels sufficient for altering or determining their charge states,

a second voltage different from the first voltage to each of two control gate lines adjacent said pair of control gate lines on opposite sides thereof in the first direction in order to maintain voltage levels of charge storage elements in second and third rows on opposite sides of said at least the first row at levels insufficient for altering or determining their states, and

(c) third voltages being connected with the plurality of bit lines sufficient for altering or determining their charge states.

9. The memory system of claim 8, wherein the charge states number in excess of two, thereby enabling more than one bit of data to be stored in each memory cell.

10. The memory system of either one of claims 8 or 9, wherein the charge storage elements are conducive floating gates.

11. The memory system of either one of claims 8 or 9, wherein the control gate lines positioned between adjacent charge storage elements are additionally capacitively coupled with regions of the substrate between the charge storage elements in a manner to affect conductivity of the substrate regions in response to voltages placed on the control gate lines.

12. The memory cell array of claim 11, wherein the control gate lines extend into trenches formed in the regions of the substrate between the charge storage elements, a layer of dielectric being positioned between the control gate lines and surfaces of the trenches.