Double density NROM with nitride strips (DDNS)

• US 7,638,835 B2
• Filed: 12/28/2006
• Issued: 12/29/2009
• Est. Priority Date: 02/28/2006
• Status: Expired due to Fees

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Irani, Rustom, Eitan, Boaz, Bloom, Ilan, Shappir, Assaf
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US11/646,430
• Publication Number:
  US 20070200180A1
• Time in Patent Office: 1,097 Days
• Field of Search: 257/324, 257/E29.309
• US Class Current: 257/324
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.

Claims

1. Non-volatile memory (NVM) cell comprising:

an ONO layer disposed on a semiconductor substrate and comprising a plurality (n) of ONO stacks;

for a given memory cell, a gate formed atop a portion of a given ONO stack and an adjacent portion of another ONO stack;

a first set of word lines disposed atop of a first set of gates;

a second set of word lines disposed atop of a second set of gates;

wherein the word lines of said first set have a width different from word lines of said second set.

2. The NVM cell of claim 1, further comprising:

vestiges of a sacrificial poly layer on outer edges of the ONO stacks.

3. The NVM cell of claim 1, wherein:

the NVM cell is an NROM cell.