Power semiconductor devices and methods of manufacture

• US 7,638,841 B2
• Filed: 05/31/2006
• Issued: 12/29/2009
• Est. Priority Date: 05/20/2003
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Challa, Ashok
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US11/445,020
• Publication Number:
  US 20060214221A1
• Time in Patent Office: 1,308 Days
• Field of Search: 257/341
• US Class Current: 257/341
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 : with a recessed gate
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 : with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/00 : Conversion of dc power input into dc power output
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Claims

1. A semiconductor device comprising:

a drift region of a first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

an active trench extending through the well region and into the drift region, the active trench having its sidewalls and bottom lined with dielectric material, and the active trench being substantially filled with a first conductive layer, a second conductive layer and a first gate conductive layer, the first conductive layer being disposed below the first gate conductive layer and separated from the gate electrode by an inter-electrode dielectric material, the second conductive layer being disposed below the first conductive layer and separated from the first conductive layer by the inter-electrode dielectric material;

source regions having the first conductivity type formed in the well region adjacent the active trench; and

a first Schottky structure formed on a first mesa between two adjacent trenches;

wherein the two adjacent trenches, between which the first Schottky structure is formed, are substantially filled with the first conductive layer, the second conductive layer and the first gate conductive layer.

2. The semiconductor device of claim 1 wherein the first conductive layer is configured to be a shield electrode.

3. The semiconductor device of claim 1 wherein the first conductive layer is configured to be a second gate electrode.

4. The semiconductor device of claim 1 wherein the second conductive layer is configured to be a shield electrode.

5. The semiconductor device of claim 1 wherein the first conductive layer is configured to be electrically biased to a potential and the second conductive layer is configured to be electrically biased to a potential.

6. The semiconductor device of claim 1 further comprising a second Schottky structure formed on a second mesa adjacent the first mesa.

7. The semiconductor device of claim 1 wherein the first Schottky structure is formed in a manner that is perpendicular to a longitudinal axis of the two adjacent trenches.

8. A semiconductor device comprising:

a drift region of a first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

a plurality of trenches extending through the well region and into the drift region, each of the plurality of trenches having its sidewalls and bottom lined with dielectric material, and each of the plurality of trenches being substantially filled with a first conductive layer, a second conductive layer, and a third conductive layer, the second conductive layer being disposed below the first conductive layer and separated from the first conductive layer by an inter-electrode dielectric material, the third conductive layer being disposed below the second conductive layer and separated from the second conductive layer by the inter-electrode dielectric material;

source regions having the first conductivity type formed in the well region adjacent a trench; and

a first Schottky structure formed on a first mesa between two adjacent trenches of the plurality of trenches;

wherein the two adjacent trenches, between which the first Schottky structure is formed, are substantially filled with the first conductive layer, the second conductive layer and the third conductive layer.

9. The semiconductor device of claim 8 wherein in active trenches the first conductive layer is configured to be a gate electrode and the second conductive layer is configured to be a shield electrode.

10. The semiconductor device of claim 8 wherein the first Schottky structure comprises a layer of Schottky barrier metal extending over the first mesa and the two adjacent trenches.

11. The semiconductor device of claim 10 wherein the layer of Schottky barrier metal is configured to electrically couple to the first conductive layer in the two adjacent trenches.

12. The semiconductor device of claim 11 wherein the layer of Schottky barrier metal is configured to electrically couple to the source regions.

13. The semiconductor device of claim 8 wherein the second conductive layer in each of the two adjacent trenches are configured to electrically couple together.

14. The semiconductor device of claim 8 further comprising a second Schottky structure formed on a second mesa adjacent the first mesa.

15. The semiconductor device of claim 14 wherein the first mesa and the second mesa are formed by three adjacent trenches, and wherein the first conductive layer in each of the three adjacent trenches are configured to electrically couple to the source regions and the second conductive layer in each of the three adjacent trenches are configured to electrically couple together.

16. The semiconductor device of claim 13 wherein the second electrodes in the active trenches are configured to electrically couple to the source regions at a periphery of the device, while the second electrodes in the two adjacent trenches are configured to electrically couple to the source regions in the middle of the device.

17. The semiconductor device of claim 8 further comprising a plurality of Schottky structures interspersed between the plurality of trenches, wherein each Schottky structure is formed on a mesa between two adjacent trenches.