Devices and systems including the bit lines and bit line contacts

• US 7,638,878 B2
• Filed: 04/13/2006
• Issued: 12/29/2009
• Est. Priority Date: 04/13/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Primary Examiner(s): Weiss; Howard
• Application Number:
  US11/404,209
• Publication Number:
  US 20070241378A1
• Time in Patent Office: 1,356 Days
• Field of Search: 257/758, 257/E21.682, 257/E21.69
• US Class Current: 257/758
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels increases processing latitude, particularly the spacing between the bit lines which, with conventional processes, may strain photolithographic limits. A semiconductor device formed using the method, and an electronic system comprising the semiconductor device, are also described.

Claims

1. A semiconductor device comprising:

a semiconductor wafer;

first bit lines, wherein each of the first bit lines has an upper surface and a lower surface, with the upper surface being more outwardly located on the semiconductor wafer than the lower surface; and

a second bit line, wherein the second bit line has an upper surface and a lower surface, with the upper surface thereof being more outwardly located on the semiconductor wafer than the lower surface, and wherein the upper surface of the second bit line is more outwardly located on the semiconductor wafer than the upper surfaces of the first bit lines,

wherein the first bit lines are each adjacent to the second bit line and the second bit line is configured to be selectively coupled to a memory cell other than memory cells to which the first bit lines are configured to be selectively coupled.

2. The semiconductor device of claim 1, wherein the lower surface of the second bit line is more outwardly located on the semiconductor wafer than the lower surfaces of the first bit lines.

3. The semiconductor device of claim 1, wherein the lower surface of the second bit line is more outwardly located on the semiconductor wafer than the upper surface of the first bit line.

4. The semiconductor device of claim 1 further comprising:

a second bit line contact electrically coupled to the second bit line and to the semiconductor wafer, wherein the second bit line contact is interposed directly between the first bit lines.

5. The semiconductor device of claim 1, wherein the second bit line is self-aligned to the first bit lines.

6. A semiconductor device comprising:

a semiconductor wafer;

a first bit line, wherein the first bit line has an upper surface and a lower surface, with the upper surface being more outwardly located on the semiconductor wafer than the lower surface; and

a second bit line, wherein the second bit line has an upper surface and a lower surface, with the upper surface thereof being more outwardly located on the semiconductor wafer than the lower surface, and wherein the upper surface of the second bit line is more outwardly located on the semiconductor wafer than the upper surface of the first bit line,

wherein the first bit line is adjacent to the second bit line and wherein the lower surface of the second bit line is at about the elevation with respect to the semiconductor wafer as the lower surface of the first bit line.

7. A semiconductor device comprising:

a first cross-sectional location, comprising;

a plurality of first and second doped regions;

a first plurality of bit line plugs contacting the first doped regions, wherein no bit line plug contacts any of the second doped regions at the first cross-sectional location;

a plurality of first bit lines contacting the plurality of bit line plugs; and

a plurality of second bit lines, wherein a lower surface of the second bit lines is above an upper surface of the first bit lines;

a second cross-sectional location comprising;

a plurality of first and second doped regions;

a second plurality of bit line plugs contacting the second doped regions, wherein no bit line plug contacts any of the first doped regions at the second cross-sectional location;

the plurality of first bit lines being continuous from the plurality of first bit lines at the first cross-sectional location; and

a plurality of second bit lines contacting the plurality of bit line plugs at the second cross-sectional location, wherein an upper surface of the second bit lines is above an upper surface of the first bit lines, wherein each of the plurality of second bit lines at the second cross-sectional location comprises a single conductive layer which extends from between adjacent first bit lines to a level above an upper level of the first bit lines, and

further comprising a conductive enhancement layer interposed between the single conductive layer and the second bit line plug, wherein each second bit line is electrically coupled to one of the second bit line plugs through the enhancement layer.

8. A semiconductor device comprising:

a first cross-sectional location, comprising;

a plurality of first and second doped regions;

a first plurality of bit line plugs contacting the first doped regions, wherein no bit line plug contacts any of the second doped regions at the first cross-sectional location;

a plurality of first bit lines contacting the plurality of bit line plugs; and

a plurality of second bit lines, wherein a lower surface of the second bit lines is above an upper surface of the first bit lines;

a second cross-sectional location comprising;

a plurality of first and second doped regions;

a second plurality of bit line plugs contacting the second doped regions, wherein no bit line plug contacts any of the first doped regions at the second cross-sectional location;

the plurality of first bit lines being continuous from the plurality of first bit lines at the first cross-sectional location; and

a plurality of second bit lines contacting the plurality of bit line plugs at the second cross-sectional location, wherein an upper surface of the second bit lines is above an upper surface of the first bit lines, and

wherein the plurality of first bit line plugs at the first cross-sectional location each comprise;

a first plug portion comprising a first conductive layer which contacts a respective one of the first doped regions; and

a second plug portion comprising a second conductive layer which contacts the first plug portion and is electrically coupled to the respective first doped region through the first plug portion, wherein a respective one of the first bit lines is electrically coupled to the respective first doped region through the second plug portion and the first plug portion.

9. The semiconductor device of claim 8, wherein the first plug portion is formed to a different dimension than the second plug portion.

10. A semiconductor device comprising:

a first cross-sectional location, comprising;

a plurality of first and second doped regions;

a first plurality of bit line plugs contacting the first doped regions, wherein no bit line plug contacts any of the second doped regions at the first cross-sectional location;

a plurality of first bit lines contacting the plurality of bit line plugs; and

a plurality of second bit lines, wherein a lower surface of the second bit lines is above an upper surface of the first bit lines;

a second cross-sectional location comprising;

a plurality of first and second doped regions;

a second plurality of bit line plugs contacting the second doped regions, wherein no bit line plug contacts any of the first doped regions at the second cross-sectional location;

the plurality of first bit lines being continuous from the plurality of first bit lines at the first cross-sectional location; and

a plurality of second bit lines contacting the plurality of bit line plugs at the second cross-sectional location, wherein an upper surface of the second bit lines is above an upper surface of the first bit lines,

further comprising,

at a third cross-sectional location, a source local interconnect comprising a conductive layer which also provides the first and second plurality of bit line plugs.

11. A semiconductor device, comprising:

a semiconductor wafer substrate assembly comprising a semiconductor wafer;

first bit line plugs at a first cross-sectional location and second bit line plugs at a second cross-sectional location;

a plurality of first bit lines at both the first and second cross-sectional locations, wherein the first bit lines contact the first bit line plugs at the first cross-sectional location but do not contact the second bit line plugs at the second cross-sectional location;

a plurality of second bit lines at both the first and second cross-sectional locations, wherein the second bit lines contact the second bit line plugs at the second cross-sectional location but do not contact the first bit line plugs at the first cross-sectional location, wherein an upper surface of the second bit lines at both the first and second cross-sectional locations is more outwardly located on the semiconductor wafer than an upper surface of the first bit lines,

wherein each of the plurality of bit lines can be selectively coupled to a different memory cell.

12. The semiconductor device of claim 11 wherein a bottom surface of the second bit lines at the first cross-sectional location is more outwardly located than an upper surface of the first bit lines at the first cross-sectional location.

13. The semiconductor device of claim 11 wherein at least one second bit line is interposed between two adjacent first bit lines at the second cross-sectional location, but the at least one second bit line is not interposed between the two adjacent first bit lines at the first cross-sectional location.

14. The semiconductor device of claim 11 further comprising:

the second bit lines comprising;

a first conductive layer which contacts the second bit line plugs at the second cross-sectional location;

a second conductive layer which contacts the first conductive layer at the second-cross-sectional location, wherein a bottom surface of the second conductive layer at the first cross-sectional location is more outwardly located on the semiconductor wafer than an upper surface of the first bit lines at the first cross-sectional location.

15. The semiconductor device of claim 11, wherein the second bit lines are self-aligned to the first bit lines.

16. The semiconductor device of claim 15, wherein each of the second bit lines at the second cross-sectional location comprises a first portion and a second portion, wherein the second portion of a respective one of the second bit lines is self-aligned to an adjacent one of the first bit lines.

17. The semiconductor device of claim 16, wherein the second portion of each of the second bit lines at the second cross-sectional location is separated from the adjacent one of the first bit lines by a respective spacer.

18. The semiconductor device of claim 17, wherein an edge of each respective spacer at least nearly aligns with an edge of the one of the second bit line plugs that contacts the respective one of the bit lines.

19. A semiconductor device memory array, comprising:

a first conductive bit line comprising at least one first conductive layer that can be selectively electrically coupled with a first plurality of memory cells; and

second conductive bit lines, each of which is adjacent to the first bit line, comprising at least one second conductive layer, wherein a first one of the second bit lines can be selectively electrically coupled with a second plurality of memory cells and a second one of the second bit lines can be selectively electrically coupled with a third plurality of memory cells, wherein the at least one second conductive layer is a different layer than the at least one first conductive layer and the first plurality of memory cells are not either of the second and third plurality of memory cells.

20. The memory array of claim 19, wherein the memory array comprises a portion of a NAND memory device.

21. The memory array of claim 19 further comprising:

at least a first bit line contact plug which electrically couples the first conductive bit line to a first conductively doped region in a semiconductor wafer section; and

at least a second bit line contact plug which electrically couples one of the second conductive bit lines to a second conductively doped region in the semiconductor wafer section.

22. The memory array of claim 21 wherein the first and second bit line contact plugs comprise a staggered arrangement.

23. An electronic device comprising:

at least one semiconductor device having a cross section comprising;

a semiconductor wafer;

first bit lines, wherein each of the first bit lines has an upper surface and a lower surface, with the upper surfaces being more outwardly located on the semiconductor wafer than the lower surfaces; and

a second bit line, wherein the second bit line has an upper surface and a lower surface, with the upper surface thereof being more outwardly located on the semiconductor wafer than the lower surface,

wherein at least 80% of the length of the upper surface of the second bit line is more outwardly located on the semiconductor wafer than 80% of the upper surfaces of the first bit lines and each of the first bit lines is adjacent to the second bit line, wherein each of the first bit lines is associated with a memory cell other than a memory cell associated with the second bit line.

24. The electronic device of claim 23 wherein the at least one semiconductor device is a nonvolatile memory device, and the electronic device further comprises:

at least one microprocessor in electrical communication with the nonvolatile memory device.

25. The semiconductor device of claim 23, wherein a vertically oriented edge of at least one of the second bit lines is vertically aligned with a respective vertically oriented edge of the first bit line.

26. A semiconductor device memory array, comprising:

a first bit line comprising a first conductive layer that can be selectively electrically coupled with a first plurality of memory cells; and

second bit lines comprising a second conductive layer different from the first conductive layer, wherein a first one of the second bit lines can be selectively electrically coupled with a second plurality of memory cells and a second one of the second bit lines can be selectively electrically coupled with a third plurality of memory cells, wherein the first bit line is adjacent to each of the second bit lines and the first plurality of memory cells are not either of the second and third plurality of memory cells.

27. The semiconductor device memory array of claim 26 wherein the first plurality of memory cells and the first bit line are coupled through at least one select transistor.

28. The semiconductor device memory array of claim 26 wherein the memory array comprises a portion of a NAND memory device.

29. The semiconductor device memory array of claim 26 further comprising:

at least a first bit line contact plug which electrically couples the first conductive bit line to a first conductively doped region in a semiconductor wafer section; and

at least a second bit line contact plug which electrically couples one of the second conductive bit lines to a second conductively doped region in the semiconductor wafer section.

30. The semiconductor device memory array of claim 29 wherein the first and second bit line contact plugs comprise a staggered arrangement.

31. The semiconductor device memory array of claim 29, wherein the first bit line contact plug is horizontally and vertically offset from the second bit line contact plug.

32. The semiconductor device memory array of claim 26, wherein the second bit lines are self-aligned to the first bit line.

33. The semiconductor device memory array of claim 32, wherein each of the second bit lines comprises a first portion and a second portion, wherein the second portions are self-aligned to the first bit line.

34. The semiconductor device memory array of claim 33, wherein the second portions of the second bit lines are separated from the first bit line by spacers.

35. The semiconductor device memory array of claim 34, further comprising a plug that couples one of the second bit lines to the second conductively doped region, wherein an edge of a respective one of the spacers at least nearly aligns with an edge of the plug.

36. The semiconductor device memory array of claim 33, wherein the first portions of the second bit lines are a different material than the second portions of the second bit lines.

37. The semiconductor device memory array of claim 26, wherein the first conductive layer and the second conductive layer comprise the same material.

38. The semiconductor device memory array of claim 26, further comprising a source line comprising the first conductive layer.

39. The semiconductor device memory array of claim 26, wherein a vertically oriented edge of at least one of the second bit lines is vertically aligned with a vertically oriented edge of the first bit line.

40. A memory array comprising:

a first conductive layer comprising a first bit line that can be selectively electrically coupled with a first plurality of memory cells; and

a second conductive layer comprising second bit lines, wherein a first one of the second bit lines can be selectively electrically coupled with a second plurality of memory cells and a second one of the second bit lines can be selectively electrically coupled with a third plurality of memory cells, wherein the first bit line is adjacent to each of the second bit lines and the first plurality of memory cells are not either of the second and third plurality of memory cells.

41. The memory array of claim 40 wherein the first plurality of memory cells and the first bit line are coupled through at least one select transistor.

42. The memory array of claim 40 wherein the memory array comprises a portion of a NAND memory device.

43. The memory array of claim 40 further comprising:

at least a first bit line contact plug which electrically couples the first conductive bit line to a first conductively doped region in a semiconductor wafer section; and

at least a second bit line contact plug which electrically couples one of the second conductive bit lines to a second conductively doped region in the semiconductor wafer section.

44. The memory array of claim 43 wherein the first and second bit line contact plugs comprise a staggered arrangement.