Voltage control and power factor correction in AC induction motors

• US 7,638,966 B1
• Filed: 09/03/2008
• Issued: 12/29/2009
• Est. Priority Date: 09/03/2008
• Status: Expired due to Fees

• Current Assignee: John E. Powers, John F. Davis
• Original Assignee: John E. Powers, John F. Davis
• Inventors: Pummer, Alexander
• Primary Examiner(s): Leykin; Rita
• Application Number:
  US12/203,808
• Time in Patent Office: 482 Days
• Field of Search: 318/729, 318/438, 318/809, 318/811
• US Class Current: 318/729
• CPC Class Codes: G05F 1/70 Regulating power factor; Regulating reactive current or power
• CPC Class Codes: H02J 3/1892 the arrangements being an integral part of the load, e.g. a motor, or of its control circuit
• CPC Class Codes: H02P 23/26 Power factor control [PFC]
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A voltage control circuit is disclosed. A power factor corrector may utilize the control circuit to provide power factor correction for an AC induction motor. An AC induction motor system may combine the power factor correct with an AC induction motor.

Claims

1. A power factor corrector for an AC induction motor, comprising:

a) an input filter configured to receive AC voltage from an AC voltage source and attenuate the AC voltage to produce a filtered AC voltage;

b) a current phase sampler configured to receive the filtered AC voltage from the input filter and output a current phase signal related to a phase of an AC current associated with the AC voltage;

c) a signal conditioning circuit configured to derive voltage phase information from the AC voltage and receive the current phase signal from the current phase sampler, and generate a phase signal having a magnitude proportional to a phase dislocation between the AC voltage and the current associated with the AC voltage as well as a voltage polarity signal that depends on a polarity of the AC voltage;

d) a first switch controller configured to receive the phase signal and the voltage polarity signal from the signal conditioning circuit and generate one or more polarity control signals and first and second pulse-width modulated polarity controlled chopping control signals;

e) a first voltage control circuit configured to receive the filtered AC voltage and to receive the first and second polarity control signals and the first and second chopping signals from the control amplifier and output an AC output voltage having an amplitude proportional to a duty cycle of the pulse first or second chopping signal, wherein the switch controller is configured to adjust a duty cycle of the chopping signals in response to the phase signal in a way that changes the amplitude of the AC output voltage to reduce a phase dislocation between the AC voltage and the AC current; and

f) a capacitor configured to prevent the voltage control circuit from interfering with the current phase sampler.

2. The power factor corrector in claim 1, wherein e) includes:

a first and second solid state switching device each of which includes;

i) an input terminal adapted to receive an AC voltage;

ii) an output terminal;

iii) a control terminal adapted to receive either the first or second chopping signal, wherein a value of the chopping signal determines whether electric current can flow between the input terminal and the output terminal;

a first diode having an anode and a cathode and a second diode having an anode and a cathode, wherein the output terminal of the first switch and the input terminal of the second switch are adapted to receive the filtered AC voltage from the current phase sampler, wherein the input terminal of the first solid state switching device is connected to the cathode of the first diode and the output terminal of the second solid state switching device is coupled to the anode of the second diode, wherein the anode of the first diode and the cathode of the second diode are electrically coupled to a node;

a third and fourth solid state switching device, each having;

i) an input terminal adapted to receive an AC voltage;

ii) an output terminal;

iii) a control terminal adapted to receive a polarity signal, wherein a value of the polarity signal determines whether electric current can flow between the input terminal and the output terminal; and

a third diode having an anode and a cathode and a fourth diode having an anode and a cathode, wherein the input terminal of the third solid state switching device is coupled to the cathode of the third diode and the output terminal of the fourth solid state switching device is coupled to the anode of the fourth diode, wherein the anode of the third diode and the cathode of the fourth diode are electrically coupled to the node, wherein the output terminal of the third switch and the input terminal of the fourth switch are adapted to couple to a neutral line of an AC source.

3. The power factor corrector in claim 2, wherein the voltage control circuit includes:

an inductor having first and second terminals, wherein the first terminal is coupled to the node; and

an output capacitor that is coupled to the second terminal of the inductor, wherein the output capacitor is configured to be coupled between an live terminal and a neutral terminal of an AC induction motor.

4. The power factor corrector of claim 3, further comprising a bipolar clamp coupled between the first terminal of the inductor and the neutral line, wherein the bipolar clamp comprises first and second clamp components coupled in parallel with each other, wherein:

the first clamp component comprises a first bias source coupled between a cathode of a first clamping diode and the neutral line, wherein the anode of the first clamping diode is coupled to the first terminal of the inductor; and

the second clamp component comprises a second bias source coupled between an anode of a second clamping diode and the neutral line, wherein the cathode of the second clamping diode is coupled to the first terminal of the inductor.

5. The power factor corrector of claim 4 wherein the first and second bias sources each include one or more capacitors.

6. The power factor corrector of claim 5 wherein the first and second bias sources include first and second threshold diodes, wherein each threshold diode is characterized by a threshold voltage that is larger than a peak value of the AC voltage.

7. The power factor corrector of claim 3, further comprising an energy storing circuit coupled between the anode of the first diode or between the node and the cathode of the second diode, wherein the energy storing system is configured to reduce a crowbar current in the third or fourth diodes during a reverse recovery time after a polarity of the AC voltage changes.

8. The power factor corrector of claim 7 wherein the energy storing circuit includes a storage inductor having a primary winding coupled between the node and the anode of the first diode or between the node and the cathode of the second diode and a magnetically permeable core inductively coupled to the winding, wherein the primary winding and the core are selected such that a voltage time integral for storage inductor is characterized by a dissipation time for a reverse bias that is greater than a reverse recovery time of the first or second diode to which the winding is coupled.

9. The power factor corrector of claim 8, further comprising a kickback diode coupled in parallel with the primary winding of the storage inductor.

10. The power factor corrector of claim 8, further comprising a secondary winding that is inductively coupled to the core and a fifth diode and load coupled in series with the secondary winding, wherein the fifth diode is configured to prevent magnetic energy stored in the core from being discharged through the secondary winding when there is a current in the primary winding and to discharge magnetic energy stored in the core when there is no current through the primary winding.

11. The power factor corrector of claim 1, further comprising a first energy storing circuit coupled between the node and the anode of the first diode and a second energy storing circuit coupled between the node and the cathode of the second diode, wherein the first and second energy storing circuits are configured to reduce crowbar current in the third and fourth diodes during a reverse recovery time.

12. The power factor corrector of claim 11 wherein the first energy storing circuit includes a first storage inductor having a first primary winding coupled between the node and the anode of the first diode and a magnetically permeable first core inductively coupled to the first primary winding, wherein the first primary winding and the first core are selected such that a voltage time integral for first storage inductor is characterized by a dissipation time for a reverse bias that is greater than a reverse recovery time of the first diode.

13. The power factor corrector of claim 12, wherein the first energy storing circuit further includes a first secondary winding that is inductively coupled to the first core and a fifth diode and first load coupled in series with the third winding, wherein the fifth diode is configured to prevent magnetic energy stored in the first core from being discharged through the first secondary winding when there is a current in the first primary winding and to discharge magnetic energy stored in the first core when there is no current through the first primary winding.

14. The power factor corrector of claim 13, wherein the second energy storing circuit includes a second storage inductor having a second primary winding coupled between the node and the cathode of the second diode and a magnetically permeable second core inductively coupled to the second primary winding, wherein the second primary winding and the second core are selected such that a voltage time integral for second storage inductor is characterized by a dissipation time for a reverse bias that is greater than a reverse recovery time of the second diode.

15. The power factor corrector of claim 14, wherein the second energy storing circuit further includes a second secondary winding that is inductively coupled to the second core and a sixth diode and a second load coupled in series with the second secondary winding, wherein the sixth diode is configured to prevent magnetic energy stored in the second core from being discharged through the second secondary winding when there is a current in the second primary winding and to discharge magnetic energy stored in the second core when there is no current through the second primary winding.

16. The power factor corrector of claim 3, wherein the energy storing system further comprises:

a first transformer having a primary winding coupled between the anode of the first diode and the first node, the first transformer having a secondary winding coupled in a first series circuit with a fifth diode and a first resistor; and

a second transformer having a primary winding coupled between the cathode of the second diode and the first node, the second transformer having a secondary winding connected in a second series circuit with a sixth diode and a second resistor.

17. The power factor corrector of claim 16 wherein the fifth diode, first resistor and the secondary winding of the first transformer are selected such that the first series circuit is characterized by a time constant that is less than a reverse recovery time for the third diode.

18. The power factor corrector of claim 17 wherein the sixth diode, second resistor and the secondary winding of the second transformer are selected such that the second series circuit is characterized by a time constant that is less than a reverse recovery time for the fourth diode.

19. The power factor corrector of claim 1, further comprising:

a) a current sample summing device configured to receive first, second and third current amplitude signals that are respectively proportional to current amplitudes of first, second and third phases of an AC power input to a three-phase AC induction motor, output a summed current amplitude signal, wherein the first phase is coupled to the current phase sampler;

b) first, second and third current amplitude samplers coupled to the current sample summing device, wherein the first, second and third, current amplitude samplers are configured to receive AC voltages for first, second and third phases of an AC power input to a three-phase AC induction motor and respectively produce the first, second and third current amplitude signals;

c) a current reference device configured to receive the summed current amplitude signal from the current sample summing device and output the summed current amplitude signal divided by three;

d) first and second current comparators each configured to receive the summed current amplitude signal divided by three from the current reference device, wherein the first current comparator receives the second current amplitude signal and outputs a first amplitude difference signal proportional a difference between the second current amplitude signal and the summed current amplitude signal divided by three, wherein the second current comparator receives the third current amplitude signal and outputs second amplitude difference signal proportional a difference between the third current amplitude signal and the summed current amplitude signal divided by three;

e) second and third switch controllers configured respectively to receive the first and second amplitude difference signals and generate one or more pulse-width modulated polarity controlled switch control signals; and

f) second and third voltage control circuits each configured to receive and the one or more pulse-width modulated polarity controlled switch control signals from the second and third switch controllers and output second and third sinusoid voltages corresponding to the second and third phases, wherein the second and third sinusoid voltages are characterized by amplitudes proportional to duty cycles of the pulse width modulated polarity controlled switch control signals from the second and third switch controllers and the mechanical load of the AC induction motor, whereby the power factor controller may control the power factor of each phase of the three-phase AC induction motor.

20. An AC induction motor system, comprising:

a) an AC induction motor;

b) an input filter configured to receive AC voltage from an AC voltage source and attenuate the AC voltage to produce an attenuated AC voltage;

c) a current phase sampler configured to receive the attenuated AC voltage from the input filter and output a current phase signal related to an AC current associated with the AC voltage;

d) a signal conditioning circuit configured to derive voltage phase information from the AC voltage and receive the current phase signal from the current phase sampler, and generate a phase signal having a magnitude proportional to a phase dislocation between a voltage of the AC voltage and the current associated with the AC signal as well as a voltage polarity signal that depends on a polarity of the AC voltage;

e) a switch controller configured to receive the phase signal and the voltage polarity signal from the signal conditioning circuit and generate one or more polarity control signals and first and second pulse-width modulated polarity controlled chopping control signals;

f) a voltage control circuit configured to receive the filtered AC voltage and to receive the first and second polarity control signals and the first and second chopping signals from the control amplifier and output an AC output voltage having an amplitude proportional to a duty cycle of the pulse first or second chopping signal, wherein the switch controller is configured to adjust a duty cycle of the chopping signals in response to the phase signal in a way that changes the amplitude of the AC output voltage to reduce a phase dislocation between the AC voltage and the AC current; and

g) a capacitor configured to prevent the voltage control circuit from interfering with the current phase sampler.

21. The system of claim 20 wherein the voltage control circuit comprises

a first and second solid state switching device each of which includes:

i) an input terminal;

ii) an output terminal;

iii) a control terminal adapted to receive a chopping signal, wherein a value of the chopping signal determines whether electric current can flow between the input terminal and the output terminal;

a first diode having an anode and a cathode and a second diode having an anode and a cathode, wherein the output terminal of the first switch and the input terminal of the second switch are adapted to receive the filtered AC voltage from the current phase sampler, wherein the input terminal of the first solid state switching device is connected to the cathode of the first diode and the output terminal of the second solid state switching device is coupled to the anode of the second diode, wherein the anode of the first diode and the cathode of the second diode are electrically coupled to a node;

a third and fourth solid state switching device, each having;

i) an input terminal adapted to receive an AC voltage;

ii) an output terminal;

iii) a control terminal adapted to receive a polarity signal, wherein a value of the polarity signal determines whether electric current can flow between the input terminal and the output terminal; and

a third diode having an anode and a cathode and a fourth diode having an anode and a cathode, wherein the input terminal of the third solid state switching device is coupled to the cathode of the third diode and the output terminal of the fourth solid state switching device is coupled to the anode of the fourth diode, wherein the anode of the third diode and the cathode of the fourth diode are electrically coupled to the node, wherein the output terminal of the third switch and the input terminal of the fourth switch are adapted to couple to a neutral line of an AC source.

22. The system of claim 21, further comprising a bipolar clamp coupled between the first terminal of the inductor and the neutral line, wherein the bipolar clamp comprises first and second clamp components coupled in parallel with each other, wherein:

a) the first clamp component comprises a first bias source coupled between a cathode of a first clamping diode and the neutral line, wherein the anode of the first clamping diode is coupled to the first terminal of the inductor; and

b) the second clamp component comprises a second bias source coupled between an anode of a second clamping diode and the neutral line, wherein the cathode of the second clamping diode is coupled to the first terminal of the inductor.

23. The system of claim 22 wherein the first and second bias sources each include one or more capacitors.

24. The system of claim 23 wherein the first and second bias sources include first and second threshold diodes, wherein each threshold diode is characterized by a threshold voltage that is larger than a peak value of the AC voltage.

25. The system of claim 21, further comprising an energy storing circuit coupled between the node and the anode of the first diode or between the node and the cathode of the second diode, wherein the energy storing system is configured to reduce a crowbar current in the third or fourth diodes during a reverse recovery time after a polarity of the polarity control signal changes.

26. The system of claim 25 wherein the energy storing circuit includes a storage inductor having a primary winding coupled between the node and the anode of the first diode or between the node and the cathode of the second diode and a magnetically permeable core inductively coupled to the primary winding, wherein the primary winding and the core are selected such that a voltage time integral for storage inductor is characterized by a dissipation time for a reverse bias that is greater than a reverse recovery time of the first or second diode to which the winding is coupled.

27. The system of claim 26, further comprising a kickback diode coupled in parallel with the primary winding of the storage inductor.

28. The system of claim 26, further comprising a secondary winding that is inductively coupled to the core and a fifth diode and load coupled in series with the secondary winding, wherein the fifth diode is configured to prevent magnetic energy stored in the core from being discharged through the secondary winding when there is a current in the primary winding and to discharge magnetic energy stored in the core when there is no current through the primary winding.

29. The system of claim 21, further comprising a first energy storing circuit coupled between the node and the anode of the first diode and a second energy storing circuit coupled between the node and the cathode of the second diode, wherein the first and second energy storing circuits are configured to reduce crowbar currents in the third and fourth diodes during a reverse recovery time.

30. The system of claim 29, wherein the first energy storing circuit comprises a first storage inductor having a first primary winding coupled between the node and the anode of the first diode and a magnetically permeable first core inductively coupled to the first primary winding, wherein the first primary winding and the first core are selected such that a voltage time integral for first storage inductor is characterized by a dissipation time for a reverse bias that is greater than a reverse recovery time of the first diode.

31. The system of claim 30, wherein the first energy storing circuit further comprises a first secondary winding that is inductively coupled to the first core and a fifth diode and first load coupled in series with the third winding, wherein the fifth diode is configured to prevent magnetic energy stored in the first core from being discharged through the first secondary winding when there is a current in the first primary winding and to discharge magnetic energy stored in the first core when there is no current through the first primary winding.

32. The system of claim 31, wherein the second energy storing circuit further comprises a second storage inductor having a second primary winding coupled between the node and the cathode of the second diode and a magnetically permeable second core inductively coupled to the second primary winding, wherein the second primary winding and the second core are selected such that a voltage time integral for second storage inductor is characterized by a dissipation time for a reverse bias that is greater than a reverse recovery time of the second diode.

33. The system of claim 32, wherein the second energy storing circuit further comprises a second secondary winding that is inductively coupled to the second core and a sixth diode and second load coupled in series with the second secondary winding, wherein the sixth diode is configured to prevent magnetic energy stored in the second core from being discharged through the second primary winding when there is a current in the second primary winding and to discharge magnetic energy stored in the second core when there is no current through the second primary winding.

34. The system of claim 25, wherein the energy storing circuit further comprises:

a) a first transformer having a primary winding coupled between the anode of the first diode and the first node, the first transformer having a secondary winding coupled in a first series circuit with a fifth diode and a first resistor; and

b) a second transformer having a primary winding coupled between the cathode of the second diode and the first node, the second transformer having a secondary winding connected in a second series circuit with a sixth diode and a second resistor.

35. The system of claim 34 wherein the fifth diode, first resistor and the secondary winding of the first transformer are selected such that the first series circuit is characterized by a time constant that is less than a reverse recovery time for the third diode.

36. The system of claim 35 wherein the sixth diode, second resistor and the secondary winding of the second transformer are selected such that the second series circuit is characterized by a time constant that is less than a reverse recovery time for the fourth diode.

37. The system of claim 21, wherein the AC induction motor is a three-phase AC induction AC motor, the system further comprising:

a) a current sample summing device configured to receive first, second and third current amplitude signals that are respectively proportional to current amplitudes of first, second and third phases of an AC power input to a three-phase AC induction motor, output a summed current amplitude signal, wherein the first phase is coupled to the current phase sampler;

b) first, second and third current amplitude samplers coupled to the current sample summing device, wherein the first, second and third, current amplitude samplers are configured to receive AC voltages for first, second and third phases of an AC power input to a three-phase AC induction motor and respectively produce the first, second and third current amplitude signals;

c) a current reference device configured to receive the summed current amplitude signal from the current sample summing device and output the summed current amplitude signal divided by three;

d) first and second current comparators each configured to receive the summed current amplitude signal divided by three from the current reference device, wherein the first current comparator receives the second current amplitude signal and outputs a first amplitude difference signal proportional a difference between the second current amplitude signal and the summed current amplitude signal divided by three, wherein the second current comparator receives the third current amplitude signal and outputs second amplitude difference signal proportional a difference between the third current amplitude signal and the summed current amplitude signal divided by three;

e) second and third switch controllers configured respectively to receive the first and second amplitude difference signals and generate one or more pulse-width modulated polarity controlled switch control signals; and

f) second and third voltage control circuits each configured to receive and the one or more pulse-width modulated polarity controlled switch control signals from the second and third switch controllers and output second and third sinusoid voltages corresponding to the second and third phases, wherein the second and third sinusoid voltages are characterized by amplitudes proportional to duty cycles of the pulse width modulated polarity controlled switch control signals from the second and third switch controllers and the mechanical load of the AC induction motor, whereby the power factor controller may control the power factor of each phase of the three-phase AC induction motor.