Structure for monitoring stress-induced degradation of conductive interconnects

• US 7,639,032 B2
• Filed: 12/19/2007
• Issued: 12/29/2009
• Est. Priority Date: 11/04/2005
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Chih-Chao, Clevenger, Lawrence A., Sullivan, Timothy D., Lee, Tom C., Gill, Jason P., McLaughlin, Paul S., Filippi, Ronald G., Li, Baozhen, Chanda, Kaushik, Agarwala, Birendra, Rathore, Hazara S., Cowley, Andrew P., Nguyen, Du B.
• Primary Examiner(s): Karlsen; Ernest F
• Application Number:
  US12/004,011
• Publication Number:
  US 20080107149A1
• Time in Patent Office: 741 Days
• Field of Search: 324/158.1, 324/537, 324/719, 324/763, 324/765, 257/48, 257/758, 257/767, 374/57
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2858 Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

Claims

1. A semiconductor chip, comprising:

a plurality of active semiconductor devices;

a dielectric material overlying the active semiconductor devices;

a plurality of metallic interconnects insulated and supported by said dielectric material, at least some of said conductive interconnects including;

a metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between said upper surface and said lower surface, said upper surface defining a horizontally extending plane, said metallic gate having a width in a widthwise direction, a length in a lengthwise direction, and a thickness in a direction of a height of said upper surface from said lower surface;

a metallic connecting line having an upper surface at least substantially level with said upper surface of said metallic plate, an inner end connected to said metallic plate at one of said peripheral edges, and an outer end horizontally displaced from said one peripheral edge, said metallic connecting line having a width much smaller than said width of said metallic plate and a length greater than said width of said metallic plate;

a metal feature disposed at a wiring level higher than said metallic connecting line; and

an upper metallic via connected with said metal feature and extending through said dielectric material, said upper metallic via having a bottom end in contact with said metallic connecting line at a location horizontally displaced from said one peripheral edge by at least about 3 microns (μ

m).

2. The semiconductor chip as claimed in claim 1, wherein the metal consists essentially of at least one metal selected from the group consisting of copper (Cu), aluminum (Al), gold (Au), and silver (Ag), the vias and lines contain liner materials selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN) and tungsten (W), and the dielectric material is selected from the group consisting of silicon dioxide (SiO₂), carbon-doped oxide (SiCOH) and a polymer.

3. The semiconductor chip as claimed in claim 1, wherein the structure is formed by a dual damascene process.

4. The semiconductor chip as claimed in claim 1, wherein a length of said metallic connecting line is greater than about ten times said width of said metallic connecting line.

5. The semiconductor chip as claimed in claim 1, wherein said bottom end contacts said metallic connecting line at a location horizontally displaced from said one peripheral edge by at least 10 microns.

6. The semiconductor chip as claimed in claimed 1, wherein said metallic plate has a plurality of dielectric filled openings extending vertically between said upper surface and said lower surface.

7. The semiconductor chip as claimed in claim 6, wherein said plurality of dielectric filled openings are arranged as a plurality of parallel elongated openings in said lengthwise direction such that said metallic plate has a plurality of parallel elongated branches extending in said lengthwise direction.