Ultra low area overhead retention flip-flop for power-down applications

• US 7,639,056 B2
• Filed: 05/26/2005
• Issued: 12/29/2009
• Est. Priority Date: 05/26/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Scott, David B., Mair, Hugh T., Ko, Uming, Gururajarao, Sumanth Katte
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US11/138,788
• Publication Number:
  US 20060267654A1
• Time in Patent Office: 1,678 Days
• Field of Search: None
• US Class Current: 327/202
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H04W 52/0283 with sequential power up or power down of successive circuit blocks, e.g. switching on the local oscillator before RF or mixer stages
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.

Claims

1. A data retention apparatus comprising:

a first latch for latching a data input;

a second latch coupled to the first latch for retaining the data input while the first latch is inoperative in a standby power mode; and

a controller having a clock input and a retention input, the controller providing a clock output to the first latch and to the second latch, wherein a change in a retention signal received at the retention input is indicative of a transition to the standby power mode, wherein the controller holds the clock output at a predefined voltage level in the standby power mode, and wherein the controller includes;

a first switch controlled by an inverse of the retention signal, wherein the first switch is inoperative in the standby power mode; and

a second switch controlled by the inverse of the retention signal, wherein the second switch holds the clock output at the predefined voltage level responsive to the inverse of the retention signal.

2. The data retention apparatus of claim 1, wherein the first latch receives power from a first power line, wherein the second latch receives power from a second power line different than the first power line, wherein each one of the first power line and the second power line has a scalable supply voltage.

3. The data retention apparatus of claim 2, wherein the first power line is switched off responsive to the change in the retention signal, wherein the switch off in the first power line causes the first latch to become inoperative.

4. The data retention apparatus of claim 2, wherein a power management controller (PMC) changes the retention signal in response to a request to change a power mode, wherein the second power line continues to provide power to the PMC in the standby power mode.

5. The data retention apparatus of claim 2, wherein the clock output is held at the predefined voltage level when the first power line is switched off.

6. The data retention apparatus of claim 1, wherein the transition is from an active power mode to the standby power mode.

7. The data retention apparatus of claim 1, comprising:

a third switch controlled by the retention signal, wherein the third switch is inoperative in the standby power mode, wherein the first switch is closed and the third switch is open during an active power mode.

8. The data retention apparatus of claim 1, wherein an area overhead associated with the first switch and the second switch is approximately 10% greater compared to a flip-flop without data retention.

9. The data retention apparatus of claim 7, wherein the first switch and the third switch are inoperable during the standby power mode.

10. The data retention apparatus of claim 7, wherein an area overhead associated with the first switch, the second switch and the third switch is approximately 15% greater compared to a flip-flop without data retention.

11. The data retention apparatus of claim 1, wherein the clock output is released from the predefined voltage level in response to another change in the retention signal.

12. The device of claim 1, included in a logic component wherein the logic component includes one of a microprocessor, a digital signal processor, a radio frequency chip, a memory and a microcontroller.

13. The device of claim 1, wherein an area overhead associated with the data retention component is approximately 10% greater compared to a flip-flop without data retention.