Circuit board structure with embedded electronic components

• US 7,639,473 B2
• Filed: 10/26/2007
• Issued: 12/29/2009
• Est. Priority Date: 12/22/2006
• Status: Active Grant

• Current Assignee: Phoenix Precision Technology Corporation (Unimicron Technology Corporation)
• Original Assignee: Phoenix Precision Technology Corporation (Unimicron Technology Corporation)
• Inventors: Hsu, Shih-Ping, Chia, Kan-Jung
• Primary Examiner(s): Lee, Jinhee J
• Assistant Examiner(s): Chen, XiaoLiang
• Application Number:
  US11/925,590
• Publication Number:
  US 20080151518A1
• Time in Patent Office: 795 Days
• Field of Search: 361/260, 361/306.3, 361/311, 361/312, 361/760, 361/763, 361/765, 174260-262, 174/258
• US Class Current: 361/260
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15787 Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/18162 of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/09309 : Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/09536 : Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2203/0315 : Oxidising metal
• CPC Class Codes: H05K 3/429 : Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: H05K 3/445 : having insulated holes or insulated via connections through the metal core
• CPC Class Codes: H05K 3/4608 : comprising an electrically conductive base or core
• CPC Class Codes: H05K 3/4641 : having integrally laminated metal sheets or special power cores

Abstract

A circuit board structure with embedded electronic components includes: a carrier board having an adhesive layer with two surfaces formed with first and second metal oxide layers covered by first and second metal layers and having at least one through hole; at least one semiconductor chip received in the through hole of the carrier board; an adhesive material filling a gap between the through hole and the semiconductor chip so as to secure the semiconductor chip in position to the through hole; a high dielectric material layer formed outwardly on the second metal layer; and at least one electrode board formed outwardly on the high dielectric material layer such that a capacitance component is formed with the second metal layer, high dielectric material layer, and electrode board. Accordingly, the capacitance component is integrated into the circuit board structure.

Claims

1. A circuit board structure with embedded electronic components, the circuit board structure comprising:

a carrier board comprising an adhesive layer integrated between first and second metal oxide layers, wherein a first metal layer is on the first metal oxide layer, and a second metal layer is on the second metal oxide layer, and wherein the carrier board defines at least one through hole, and the at least one through hole penetrates through the adhesive layer, first and second metal oxide layers, and first and second metal layers;

at least one semiconductor chip received in the at least one through hole of the carrier board;

an adhesive material filling a gap between the carrier board and the semiconductor chip so as to secure the semiconductor chip in position to the through hole of the carrier board;

a high dielectric material layer on the second metal layer; and

at least one electrode board on the high dielectric material layer such that the second metal layer, high dielectric material layer, and electrode board together are a capacitance component.

2. The circuit board structure of claim 1, wherein the semiconductor chip has an active surface and a non-active surface opposite to the active surface, allowing the active surface to be provided with a plurality of electrode pads and positioned at the same side with the second metal layer with respect to the carrier board.

3. The circuit board structure of claim 2, further comprising a circuit build-up structure formed on the active surface of the semiconductor chip, high dielectric material layer, and electrode board, and having a plurality of conductive structures for electrical connection with the electrode pads of the semiconductor chip and the electrode board of the capacitance component.

4. The circuit board structure of claim 3, wherein the circuit build-up structure comprises a dielectric layer, a circuit layer superimposed on the dielectric layer, and the conductive structures in the dielectric layer.

5. The circuit board structure of claim 3, wherein a plurality of electrical connection pads are on the circuit build-up structure.

6. The circuit board structure of claim 5, further comprising a solder mask covering the circuit build-up structure and defining a plurality of openings exposing the electrical connection pads of the circuit build-up structure.

7. The circuit board structure of claim 5, further comprising a plurality of conductive components mounted on the electrical connection pads.

8. The circuit board structure of claim 3, further comprising another circuit build-up structure on the first metal layer and the non-active surface of the semiconductor chip, wherein the carrier board defines at least one plated through hole electrically connecting the circuit build-up structures.

9. The circuit board structure of claim 8, wherein the another circuit build-up structure comprises a dielectric layer, a circuit layer superimposed on the dielectric layer, and a plurality of conductive structures in the dielectric layer.

10. The circuit board structure of claim 8, wherein a plurality of electrical connection pads are on the another circuit build-up structure.

11. The circuit board structure of claim 10, further comprising a solder mask covering the another circuit build-up structure and defining a plurality of openings exposing the electrical connection pads of the another circuit build-up structure.

12. The circuit board structure of claim 10, further comprising a plurality of conductive components mounted on the electrical connection pads.

13. The circuit board structure of claim 1, wherein the semiconductor chip has an active surface and a non-active surface opposite to the active surface, allowing the active surface to be provided with a plurality of electrode pads and positioned at the same side with the first metal layer with respect to the carrier board.

14. The circuit board structure of claim 13, further comprising a circuit build-up structure on surfaces of the non-active surface of the semiconductor chip, high dielectric material layer, and electrode board, and having a plurality of conductive structures for electrical connection with the electrode board of the capacitance component.

15. The circuit board structure of claim 14, wherein the circuit build-up structure comprises a dielectric layer, a circuit layer superimposed on the dielectric layer, and the conductive structures in the dielectric layer.

16. The circuit board structure of claim 14, wherein a plurality of electrical connection pads are on the circuit build-up structure.

17. The circuit board structure of claim 16, further comprising a solder mask covering the circuit build-up structure and defining a plurality of openings exposing the electrical connection pads of the circuit build-up structure.

18. The circuit board structure of claim 16, further comprising a plurality of conductive components mounted on the electrical connection pads.

19. The circuit board structure of claim 13, further comprising another circuit build-up structure on the first metal layer and the active surface of the semiconductor chip and having a plurality of conductive structures for electrical connection with the electrode pads of the semiconductor chip, wherein the carrier board defines at least one plated through hole for electrically connecting the circuit build-up structures.

20. The circuit board structure of claim 19, wherein the another circuit build-up structure comprises a dielectric layer, a circuit layer superimposed on the dielectric layer, and a plurality of conductive structures in the dielectric layer.

21. The circuit board structure of claim 19, wherein a plurality of electrical connection pads are on the another circuit build-up structure.

22. The circuit board structure of claim 21, further comprising a solder mask covering the another circuit build-up structure and defining a plurality of openings exposing the electrical connection pads of the another circuit build-up structure.

23. The circuit board structure of claim 21, further comprising a plurality of conductive components mounted on the electrical connection pads.

24. The circuit board structure of claim 1, wherein the first and second metal layers are aluminum, and the first and second metal oxide layers are aluminum oxide.

25. The circuit board structure of claim 1, wherein the adhesive layer is one of a thermosetting resin and a glue.