Phase change memory dynamic resistance test and manufacturing methods

• US 7,639,527 B2
• Filed: 01/07/2008
• Issued: 12/29/2009
• Est. Priority Date: 01/07/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation, Macronix International Co., Ltd.
• Original Assignee: International Business Machines Corporation, Macronix International Co., Ltd.
• Inventors: Rajendran, Bipin, Lee, Ming-Hsiu, Lam, Chung Hon
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US11/970,348
• Publication Number:
  US 20090175071A1
• Time in Patent Office: 722 Days
• Field of Search: 365/113
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part

Abstract

A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the resistance measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, and used for controlling manufacturing operations.

Claims

1. A method for testing an integrated circuit memory device, the memory device including memory cells comprising phase change elements having a dynamic resistance, comprising:

applying a sequence of test pulses to at least one memory cell on the device, which test pulses result in current through the memory cell having amplitude dependent on the test pulse;

measuring resistance of the memory cell in response to the sequence of test pulses;

extracting a parameter set including at least one numerical coefficient that models dependence of the measured resistance on the amplitude of the current through the memory cell; and

associating the parameter set with the device.

2. The method of claim 1, including discarding the device if the at least one numerical coefficient indicates that the device is not reliable.

3. The method of claim 1, including stopping a manufacturing process for additional devices if the at least one numerical coefficient indicates that the device is faulty.

4. The method of claim 1, including storing a record on a machine readable medium for device including or pointing to the at least one numerical coefficient.

5. The method of claim 1, wherein the sequence of test pulses comprise varying voltage pulses having magnitudes sufficient to melt a portion of the memory cell, and durations for thermal transients to settle before said measuring resistance.

6. The method of claim 1, wherein the sequence of test pulses comprise more than 2 varying voltage pulses having equal durations between about 20 and 100 nsec.

7. The method of claim 1, wherein the at least one coefficient include a slope A and an intercept B for a function of the form

R=A/I+B,

where R is the measured resistance and I is the current in the device during a test pulse in the sequence.

8. The method of claim 1, wherein the at least one coefficient include a first coefficient having a value that depends primarily on material properties of the memory cell.

9. The method of claim 1, wherein the at least one coefficient include a first coefficient having a value that depends primarily on material properties of the memory cell, and a second coefficient having a value that depends on material properties and critical dimensions of the memory cell.

10. The method of claim 1, wherein the memory cell is characterized by having a bottom electrode contacting a phase change memory element in a contact area, and by formation of a molten region during a test pulse near the bottom electrode having a volume dependent on the contact area and on current magnitude during the test.

11. The method of claim 1, including after said measuring resistance of the memory cell in response to the sequence of test pulses, subjecting the memory cell to a stress, and then

applying a second sequence of test pulses to the memory cell on the device, which test pulses result in current through the memory cell having amplitude dependent on the test pulse;

measuring resistance of the memory cell in response to the second sequence of test pulses;

extracting a second parameter set including at least one numerical coefficient that models dependence of the measured resistance on the amplitude of the current through the memory cell during the second sequence of test pulses; and

associating the second parameter set with the device.

12. The method of claim 1, wherein the memory cell is coupled to one of a bit line and a word line via an access transistor, and including biasing the access transistor in a linear region during said applying a sequence of test pulses.

13. A method for manufacturing an integrated circuit including a memory device, the memory device including memory cells comprising phase change elements having a dynamic resistance, comprising:

performing manufacturing processed to produce an integrated circuit including including a testable memory cell;

testing the testable memory cell by a test process comprising

applying a sequence of test pulses to the testable memory cell on the device, which test pulses result in current through the testable memory cell having amplitude dependent on the test pulse;

measuring a resistance of the testable memory cell in response to the sequence of test pulses;

extracting a parameter set including at least one numerical coefficient that models dependence of the measured resistance on the amplitude of the current through the testable memory cell; and

analyzing the parameter set, and performing continuing manufacturing if the parameter set meets specified guidelines, else performing at least one of the actions including discarding the integrated circuit device and suspending manufacturing process for pending analysis.

14. The method of claim 13, wherein the sequence of test pulses comprise varying voltage pulses having magnitudes sufficient to melt a portion of the testable memory cell, and durations for thermal transients to settle before said measuring resistance.

15. The method of claim 13, wherein the sequence of test pulses comprise more than 2 varying voltage pulses having equal durations between about 20 and 100 nsec.

16. The method of claim 13, wherein the extracted coefficients include a slope A and an intercept B for a function of the form

R=A/I+B,

where R is the measured resistance and I is the current in the device during a test pulse in the sequence.

17. The method of claim 13, wherein the one or more extracted coefficients include a first coefficient having a value that depends primarily on material properties of the testable memory cell.

18. The method of claim 13, wherein the one or more extracted coefficients include a first coefficient having a value that depends primarily on material properties of the testable memory cell, and a second coefficient having a value that depends on material properties and critical dimensions of the testable memory cell.

19. The method of claim 13, wherein the testable memory cell is characterized by having a bottom electrode contacting a phase change memory element in a contact area, and by formation of a molten region during a test pulse near the bottom electrode having a volume dependent on the contact area and on current magnitude during the test.

20. The method of claim 13, including after said measuring resistance of the testable memory cell in response to the sequence of test pulses, subjecting the testable memory cell to a stress, and then

applying a second sequence of test pulses to the testable memory cell, which test pulses result in current through the testable memory cell having amplitude dependent on the test pulse;

measuring resistance of the testable memory cell in response to the second sequence of test pulses;

extracting a second parameter set including at least one numerical coefficient that models dependence of the measured resistance on the amplitude of the current through the testable memory cell during the second sequence of test pulses; and

wherein said analyzing the parameter set includes comparing at least one coefficient in the parameter set extracted before said stress with a corresponding coefficient in the second parameter set.

21. The method of claim 13, wherein the memory cell is coupled to one of a bit line and a word line via an access transistor, and including biasing the access transistor in a linear region during said applying a sequence of test pulses.