Method and apparatus for partial reconfiguration circuit design for a programmable device

• US 7,640,527 B1
• Filed: 06/29/2006
• Issued: 12/29/2009
• Est. Priority Date: 06/29/2006
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Shiflet, Eric M., Dorairaj, Nij
• Primary Examiner(s): Dinh; Paul
• Assistant Examiner(s): Nguyen; Nha T
• Application Number:
  US11/478,208
• Time in Patent Office: 1,279 Days
• Field of Search: 716 8- 11, 716 16- 17, 716/4, 716/5, 716/6, 703/14
• US Class Current: 716/139
• CPC Class Codes: G06F 30/31 Design entry, e.g. editors specifically adapted for circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Method, apparatus, and computer readable medium for circuit design for a programmable device is described. In one example, a logical description of a circuit design having static logic and reconfigurable logic is imported into a graphical environment. The circuit design is processed in the graphical environment. In particular, the logical description is floorplanned to locate the static logic and the reconfigurable logic in a floorplan of the programmable device. At least one design rule check (DRC) is performed. A partial reconfiguration implementation of the circuit design is then managed for the programmable device.

Claims

1. A method of circuit design for a programmable device, comprising:

importing a logical description of a circuit design having static logic and reconfigurable logic into a graphical environment; and

processing, by using a processor, the circuit design in a graphical user interface (GUI) of the graphical environment by;

displaying a representation of the logical description in a netlist view of the GUI, a floorplan of the programmable device in a floorplan view of the GUI, and area constraints within the floorplan in a physical hierarchy view of the GUI;

floorplanning the logical description to locate the static logic and the reconfigurable logic in the floorplan of the programmable device via interaction with at least one of the netlist view, the floorplan view, or the physical hierarchy view;

performing at least one design rule check (DRC) via interaction with the netlist view, the floorplan view, and the physical hierarchy view; and

managing a partial reconfiguration implementation of the circuit design for the programmable device by;

implementing the static logic;

implementing at least one partial reconfiguration module (PRM) of the reconfigurable logic; and

assembling the static logic and the at least one PRM as implemented to generate a plurality of bitstreams including at least one full bitstream and at least one partial bitstream.

2. The method of claim 1, wherein the step of floorplanning comprises:

assigning an area in the floorplan to each of at least one partial reconfiguration module (PRM) of the reconfigurable logic; and

assigning an area in the floorplan to the static logic.

3. The method of claim 2, wherein the step of floorplanning further comprises:

placing at least one bus macro in the floorplan.

4. The method of claim 1, wherein the at least one DRC includes at least one of a bus macro DRC, a floorplanning DRC, a glitching logic DRC, or a timing advisor DRC.

5. The method of claim 1, wherein the step of processing comprises:

estimating a size of the at least one of the plurality of bitstreams.

6. The method of claim 1, wherein the step of managing further comprises:

executing a wizard of the GUI to manage the steps of implementing the static logic, implementing the at least one PRM, and assembling.

7. Apparatus for circuit design for a programmable device, comprising:

an import module for importing a logical description of a circuit design having static logic and reconfigurable logic into a graphical environment; and

a graphical environment for processing the circuit design in a graphical user interface (GUI), the graphical environment having;

a netlist view in the GUI configured to display a representation of the logical description;

a floorplan view in the GUI configured to display a floorplan of the programmable device;

a physical hierarchy view in the GUI configured to display area constraints within the floorplan;

a floorplanner for floorplanning the logical description to locate the static logic and the reconfigurable logic in the floorplan of the programmable device via interaction with at least one of the netlist view, the floorplan view, or the physical hierarchy view;

a design rule check (DRC) module for performing at least one DRC via interaction with the netlist view, the floorplan view, and the physical hierarchy view; and

an implementation flow manager for managing a partial reconfiguration implementation of the circuit design for the programmable device by;

implementing the static logic;

implementing at least one partial reconfiguration module (PRM) of the reconfigurable logic; and

assembling the static logic and the at least one PRM as implemented to generate a plurality of bitstreams including at least one full bitstream and at least one partial bitstream.

8. The apparatus of claim 7, wherein the floorplanner is configured to:

assign an area in the floorplan to each of at least one partial reconfiguration module (PRM) of the reconfigurable logic; and

assign an area in the floorplan to the static logic.

9. The apparatus of claim 8, wherein the floorplanner is further configured to:

place at least one bus macro in the floorplan.

10. The apparatus of claim 7, wherein the at least one DRC includes at least one of a bus macro DRC, a floorplanning DRC, a glitching logic DRC, or a timing advisor DRC.

11. The apparatus of claim 7, wherein the graphical environment further comprises:

a bitstream size estimator for estimating a size of the at least one of the plurality of bitstreams.

12. The apparatus of claim 7, wherein the implementation flow manager is further configured to:

execute a wizard of the GUI to manage performance of implementation of the static logic and the at least one PRM and assembly.

13. A computer readable medium having stored thereon software that, when executed by a processor, causes the processor to perform a method of circuit design for a programmable device, comprising:

importing a logical description of a circuit design having static logic and reconfigurable logic into a graphical environment; and

processing the circuit design in a graphical user interface (GUI) of the graphical environment by;

displaying a representation of the logical description in a netlist view of the GUI, a floorplan of the programmable device in a floorplan view of the GUI, and area constraints within the floorplan in a physical hierarchy view of the GUI;

floorplanning the logical description to locate the static logic and the reconfigurable logic in the floorplan of the programmable device via interaction with at least one of the netlist view, the floorplan view, or the physical hierarchy view;

performing at least one design rule check (DRC) via interaction with at least one of the netlist view, the floorplan view, and the physical hierarchy view; and

managing a partial reconfiguration implementation of the circuit design for the programmable device by;

implementing the static logic;

implementing at least one partial reconfiguration module (PRM) of the reconfigurable logic; and

assembling the static logic and the at least one PRM as implemented to generate a plurality of bitstreams including at least one full bitstream and at least one partial bitstream.

14. The computer readable medium of claim 13, wherein the step of floorplanning comprises:

assigning an area in the floorplan to each of at least one partial reconfiguration module (PRM) of the reconfigurable logic; and

assigning an area in the floorplan to the static logic.

15. The computer readable medium of claim 14, wherein the step of floorplanning further comprises:

placing at least one bus macro in the floorplan.

16. The computer readable medium of claim 13, wherein the at least one DRC includes at least one of a bus macro DRC, a floorplanning DRC, a glitching logic DRC, or a timing advisor DRC.

17. The computer readable medium of claim 13, wherein for step of processing comprises:

estimating a size of the at least one of the plurality of bitstreams.