Method for making a transducer

• US 7,642,115 B2
• Filed: 04/20/2009
• Issued: 01/05/2010
• Est. Priority Date: 05/03/2005
• Status: Active Grant

• Current Assignee: Rosemount Aerospace, Inc. (Raytheon Technologies Corporation d/b/a RTX)
• Original Assignee: Rosemount Aerospace, Inc. (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Guo, Shuwen, Childress, Kimiko J., Eriksen, Odd Harald Steen
• Primary Examiner(s): Smoot; Stephen W
• Application Number:
  US12/426,310
• Publication Number:
  US 20090203163A1
• Time in Patent Office: 260 Days
• Field of Search: 257/E29.324, 257/E21.533
• US Class Current: 438/51
• CPC Class Codes: C23C 14/021 Cleaning or etching treatments
• CPC Class Codes: C23C 14/022 by means of bombardment with energetic particles or radiation
• CPC Class Codes: C23C 14/025 Metallic sublayers
• CPC Class Codes: C23C 14/0682 Silicides
• CPC Class Codes: C23C 14/5806 Thermal treatment
• CPC Class Codes: C23C 14/5846 Reactive treatment
• CPC Class Codes: C23C 14/5873 Removal of material
• CPC Class Codes: G01L 19/0061 Electrical connection means
• CPC Class Codes: G01L 19/0069 from the sensor to its support
• CPC Class Codes: G01L 19/0076 using buried connections
• CPC Class Codes: G01L 19/0084 to the outside of the housing other details about the housing see G01L19/14
• CPC Class Codes: G01L 19/0609 Pressure pulsation damping arrangements
• CPC Class Codes: G01L 19/141 Monolithic housings, e.g. molded or one-piece housings
• CPC Class Codes: G01L 19/147 Details about the mounting of the sensor to support or covering means
• CPC Class Codes: G01L 19/148 Details about the circuit board integration, e.g. integrated with the diaphragm surface or encapsulation
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: G01L 9/0054 integral with a semiconducting diaphragm
• CPC Class Codes: G01L 9/008 using piezoelectric devices piezoelectric resonators G01L9/0022; surface acoustic waves G01L9/0025
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/45169 Platinum (Pt) as principal constituent
• CPC Class Codes: H01L 2224/48472 : the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/81805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/83805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method for forming a transducer including the step of providing a semiconductor-on-insulator wafer including first and second semiconductor layers separated by an electrically insulating layer. The method further includes depositing or growing a piezoelectric film or piezoresistive film on the wafer, depositing or growing an electrically conductive material on the piezoelectric or piezoresistive film to form at least one electrode, and depositing or growing a bonding layer including an electrical connection portion that is located on or is electrically coupled to the electrode. The method further includes the step of providing a ceramic substrate having a bonding layer located thereon, the bonding layer including an electrical connection portion and being patterned in a manner to generally match the bonding layer of the semiconductor-on-insulator wafer. The method also includes causing the bonding layer of the semiconductor-on-insulator wafer and the bonding layer of the substrate to bond together to thereby mechanically and electrically couple the semiconductor-on-insulator wafer and the substrate to form the transducer, wherein the electrical connection portions of the bonding layers of the semiconductor-on-insulator wafer and the substrate are fluidly isolated from the surrounding environment by the bonding layers.

Claims

1. A method for forming a transducer comprising the steps of:

providing a semiconductor-on-insulator wafer including first and second semiconductor layers separated by an electrically insulating layer;

depositing or growing a piezoelectric or piezoresistive film on said wafer;

depositing or growing an electrically conductive material on said piezoelectric or piezoresistive film to form at least one electrode;

depositing or growing a bonding layer including an electrical connection portion that is located on or is electrically coupled to said electrode;

providing a ceramic substrate having a bonding layer located thereon, said bonding layer including an electrical connection portion and being patterned in a manner to generally match said bonding layer of said wafer; and

causing said bonding layer of said wafer and said bonding layer of said substrate to bond together to thereby mechanically and electrically couple said wafer and said substrate to form said transducer, wherein the electrical connection portions of said bonding layers of said wafer and said substrate are fluidly isolated from the surrounding environment by said bonding layers.

2. The method of claim 1 wherein said first depositing or growing step includes epitaxially growing said piezoelectric film on said wafer.

3. The method of claim 1 wherein said transducer formed after said causing step can withstand, and continue functioning when exposed to, a temperature of 600 degrees Celsius and a pressure of 600 psig.

4. The method of claim 1 wherein said bonding layers of said wafer and said substrate form a solid solution alloy after said causing step.

5. The method of claim 1 further comprising the step of removing part of said wafer to form a generally flexible diaphragm configured to flex when exposed to a sufficient differential pressure thereacross, wherein at least part of said piezoelectric or piezoresistive film is positioned on said diaphragm, and wherein said electrode is electrically coupled to said piezoelectric or piezoresistive film.

6. The method of claim 1 wherein said wafer is a silicon-on-insulator wafer, and wherein the method further comprises removing part of said wafer to form a silicon diaphragm having a thickness of between about 3 and about 300 microns, and wherein said first depositing or growing step includes depositing or growing at least part of said piezoelectric or piezoresistive film on said diaphragm.

7. The method of claim 1 further comprising the steps of providing a connecting component and coupling said connecting component to said substrate such that said connecting component is electrically coupled to said electrical connection portion of said bonding layer of said substrate.

8. The method of claim 7 wherein the method further includes forming a hole in said substrate and positioning said connecting component in said hole.

9. The method of claim 8 wherein said hole is formed by waterjet drilling.

10. The method of claim 7 further comprising the step of planarizing at least one of said connecting component or said substrate such that said connecting component and said substrate are generally co-planar.

11. The method of claim 7 wherein an active braze material is positioned between said connecting component and said substrate to aid in connecting said connecting component to said substrate.

12. The method of claim 7 wherein said connecting component is coupled to said electrical connection portion of said bonding layer of said wafer by a solid solution alloy interposed therebetween.

13. The method of claim 7 wherein said connecting component is metallic, and wherein the connecting component is coupled to an attachment surface of said substrate by depositing an active braze material on said attachment surface, positioning said connecting component adjacent to said attachment surface with said active braze material located thereon, depositing an attachment braze material such that said attachment braze material contacts said active braze material and said connecting component to form a joint joining said connecting component and said substrate, and planarizing at least one of said connecting component or said joint such that said connecting component and said substrate are generally co-planar.

14. The method of claim 13 wherein at least one of said connecting component or said joint protrudes through said substrate prior to said planarizing step, and wherein said planarizing step removes said protruding portion of said connecting component or said joint.

15. The method of claim 1 wherein said bonding layers are located around said electrical connection portions such that said bonding layers, said substrate and said wafer form a generally sealed cavity about said electrical connection portions.

16. The method of claim 1 wherein said causing step is carried out at a bonding temperature of less than 500 degrees Celsius, and wherein said bonding layers, after said causing step, do not melt when exposed to temperatures in excess of 600 degrees Celsius.

17. The method of claim 1 wherein said causing step is carried out at a temperature that is at least a bonding temperature sufficient to cause said bonding, and wherein said bonding layers, after said causing step, do not melt when exposed to said bonding temperature.

18. The method of claim 1 wherein said bonding layers include a solid solution alloy after said causing step.

19. The method of claim 1 wherein said wafer includes a lead electrically coupled to said electrode at one end and to said electrical connection portion of said wafer at another end thereof, and wherein at least part of said lead is positioned directly between said bonding layer of said wafer and a body portion of said wafer.

20. The method of claim 1 further including the steps of positioning said substrate inside a metal ring and brazing said substrate to said ring by a braze joint, and wherein after brazing said substrate to said ring said braze joint includes a metallization layer, said metallization layer including an adhesion layer selected from the group consisting of compounds that are the reaction product of the substrate and a metal selected from the group consisting of tantalum, chromium, zirconium, and hafnium, a first diffusion blocking layer of a compound selected from the group consisting of tantalum silicide, tantalum carbide, tantalum nitride and tungsten nitride, and a second diffusion blocking layer of platinum silicide.

21. The method of claim 1 further including the steps of positioning said electrical connection portions adjacent to each other and joining said electrical connection portions by a eutectic bonding process to form a joint therebetween, and wherein after said eutectic bonding process said joint includes a metallization layer, said metallization layer including an adhesion layer selected from the group consisting of compounds that are the reaction product of the substrate and a metal selected from the group consisting of tantalum, chromium, zirconium, and hafnium, a first diffusion blocking layer of a compound selected from the group consisting of tantalum silicide, tantalum carbide, tantalum nitride and tungsten nitride, and a second diffusion blocking layer of platinum silicide.

22. The method of claim 1 further including the step of positioning said substrate in a ring such that said substrate is maintained in a state of compression inside said ring.

23. The method of claim 1 wherein said substrate includes a pair of opposed sides, and wherein said sensor die and said electrical connection portion are both located on the same side of said substrate.

24. A method for forming a transducer comprising the steps of:

providing a semiconductor-on-insulator wafer, said wafer including a piezoelectric or piezoresistive film, an electrical connection portion that is electrically coupled to said piezoelectric or piezoresistive film, and a bonding layer;

providing a substrate having a bonding layer and an electrical connection portion located thereon, said bonding layer being patterned in a manner to generally match at least part of said bonding layer of said wafer;

electrically coupling said electrical connection portions of said wafer and said substrate; and

causing said bonding layer of said wafer and said bonding layer of said substrate to bond together to thereby mechanically couple said wafer and said substrate, wherein the electrical connection portions of said wafer and said substrate are fluidly isolated from the surrounding environment by said bonding layers.

25. A method for forming a transducer comprising the steps of:

providing a semiconductor-on-insulator wafer including first and second semiconductor layers separated by an electrically insulating layer;

doping an upper layer of said wafer to form a piezoresistive film;

etching said piezoresistive film to form at least one piezoresistor;

depositing or growing a bonding layer including an electrical connection portion that is located on or is electrically coupled to said piezoresistive film;

providing a ceramic substrate having a bonding layer located thereon, said bonding layer including an electrical connection portion and being patterned in a manner to generally match said bonding layer of said wafer; and

causing said bonding layer of said wafer and said bonding layer of said substrate to bond together to thereby mechanically and electrically couple said wafer and said substrate to form said sensor, wherein the electrical connection portions of said bonding layers of said wafer and said substrate are fluidly isolated from the surrounding environment by said bonding layers.