Decoupling capacitor closely coupled with integrated circuit

• US 7,642,131 B2
• Filed: 11/08/2006
• Issued: 01/05/2010
• Est. Priority Date: 07/26/2001
• Status: Expired due to Term

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Jandzio, Gregory M., Brief, Joseph B., Beck, Donald J., Vinson, Robert S.
• Primary Examiner(s): Le; Thao X
• Assistant Examiner(s): Tran; Thanh Y
• Application Number:
  US11/557,564
• Publication Number:
  US 20070065983A1
• Time in Patent Office: 1,154 Days
• Field of Search: 257/777, 257/778, 257723-724, 257/782, 257/780, 257/784, 257/686, 361760-764, 361782-784, 361/734, 361/738, 361/811, 361/790, 438/107, 438/108, 438/109, 438/110, 438/381, 438/FOR.368
• US Class Current: 438/109
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

An integrated circuit module, decoupling capacitor assembly and method are disclosed. The integrated circuit module includes a substrate and integrated circuit die mounted on the substrate and having die pads and an exposed surface opposite from the substrate. A plurality of substrate bonding pads are positioned on the substrate adjacent the integrated circuit die. A decoupling capacitor assembly is mounted on each integrated circuit die and includes a capacitor carrier secured onto the exposed surface of the integrated circuit die and a decoupling capacitor carried by the capacitor carrier. A wire bond extends from the decoupling capacitor assembly to a die pad and from a die pad to a substrate bonding pad.

Claims

1. A method of forming an integrated circuit chip module comprising the steps of:

mounting a plurality of integrated circuit die directly on a substrate having die pads and an exposed surface opposite from the substrate, and a plurality of substrate bonding pads positioned directly on the substrate adjacent each integrated circuit die, wherein the plurality of integrated circuit die directly contact the substrate;

adhesively securing a plurality of decoupling capacitors onto a plurality of capacitor carriers to form a plurality of decoupling capacitor assemblies, wherein each capacitor carrier is formed as an aluminum nitride substrate that is about 5 mil to about 50 mil thickness, a thin film metallization layer formed directly on each capacitor carrier and a conductive adhesive layer applied directly onto the thin film metallization layer for conducting current between the capacitor and capacitor carrier and securing each decoupling capacitor onto the thin film metallization layer;

adhesively securing the plurality of decoupling capacitor assemblies in series onto each integrated circuit die; and

wire bonding from the thin film metallization layer to a logic pin on the integrated circuit die and wire bonding from the logic pin to substrate bonding pads positioned on the substrate.

2. A method according to claim 1, and further comprising the step of forming the substrate as a ceramic substrate.

3. A method according to claim 1, and further comprising the step of forming the substrate as a polymeric substrate.