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Integrated circuit having a memory cell array and method of forming an integrated circuit

  • US 7,642,572 B2
  • Filed: 04/13/2007
  • Issued: 01/05/2010
  • Est. Priority Date: 04/13/2007
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit having a memory cell array comprising:

  • memory cells;

    bitlines running along a first direction;

    wordlines running along a second direction substantially perpendicular to the first direction;

    active area segments; and

    bitline contacts, being arranged in columns extending in the second direction and in rows extending in the first direction,wherein a distance between neighboring bitlines is dL, and a distance between neighboring bitline contacts is dC, dC being measured parallel to the first direction, wherein 1/2.25≦

    dL/dC≦

    1/1.75.

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