Integrated circuit having a memory cell array and method of forming an integrated circuit
First Claim
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1. An integrated circuit having a memory cell array comprising:
- memory cells;
bitlines running along a first direction;
wordlines running along a second direction substantially perpendicular to the first direction;
active area segments; and
bitline contacts, being arranged in columns extending in the second direction and in rows extending in the first direction,wherein a distance between neighboring bitlines is dL, and a distance between neighboring bitline contacts is dC, dC being measured parallel to the first direction, wherein 1/2.25≦
dL/dC≦
1/1.75.
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Abstract
An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.
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Citations
20 Claims
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1. An integrated circuit having a memory cell array comprising:
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memory cells; bitlines running along a first direction; wordlines running along a second direction substantially perpendicular to the first direction; active area segments; and bitline contacts, being arranged in columns extending in the second direction and in rows extending in the first direction, wherein a distance between neighboring bitlines is dL, and a distance between neighboring bitline contacts is dC, dC being measured parallel to the first direction, wherein 1/2.25≦
dL/dC≦
1/1.75. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. An electronic device comprising
an interface; - and
a memory device adapted to be interfaced by the interface, wherein the memory device includes a memory cell array comprising; memory cells; bitlines running along a first direction; wordlines running along a second direction substantially perpendicular to the first direction; active area segments; and bitline contacts being arranged in columns extending in the second direction and in rows extending in the first direction, wherein a distance between neighboring bitlines is dL, and a distance between neighboring bitline contacts is dC, dC being measured parallel to the first direction, wherein 1/2.25≦
dL/dC≦
1/1.75. - View Dependent Claims (19)
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20. A computer system comprising DRAM components, each of the DRAM components comprising:
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memory cells; bitlines running along a first direction; wordlines running along a second direction substantially perpendicular to the first direction; active area segments; and bitline contacts being arranged in columns extending in the second direction and in rows extending in the first direction, wherein a distance between neighboring bitlines is dL, and a distance between neighboring bitline contacts is dC, dC being measured parallel to the first direction, wherein 1/2.25≦
dL/dC≦
1/1.75.
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Specification