Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same

• US 7,642,578 B2
• Filed: 12/16/2005
• Issued: 01/05/2010
• Est. Priority Date: 03/24/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sungyoung, Shin, Dongsuk
• Primary Examiner(s): Ha; Nathan W
• Application Number:
  US11/303,408
• Publication Number:
  US 20060216897A1
• Time in Patent Office: 1,481 Days
• Field of Search: 257/231, 257/331, 257/213, 257/288, 257/347, 257/E29.255
• US Class Current: 257/288
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A field-effect transistor (FET) with a round-shaped nano-wire channel and a method of manufacturing the FET are provided. According to the method, source and drain regions are formed on a semiconductor substrate. A plurality of preliminary channel regions is coupled between the source and drain regions. The preliminary channel regions are etched, and the etched preliminary channel regions are annealed to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape.

Claims

1. A field effect transistor (FET), comprising:

a semiconductor substrate;

source and drain regions on the semiconductor substrate, the source and drain regions comprising a stacked structure of a silicon germanium layer and a silicon layer; and

a plurality of FET channel regions coupled between the source and drain regions, the FET channel regions having a substantially circular cross-sectional shape, the FET channel regions being trimmed to a desired dimension such that a front surface of at least one of the FET channel regions is offset with respect to a front surface of the source and drain regions in a direction normal to the front surface of the source and drain regions; and

a protruding portion of the semiconductor substrate in the gate region beneath the FET channel region.

2. The field effect transistor of claim 1, further comprising a gate dielectric layer on the FET channel regions.

3. The field effect transistor of claim 1, further comprising a gate surrounding the FET channel regions.

4. The field effect transistor of claim 3, wherein the gate comprises polysilicon.

5. The field effect transistor of claim 3, wherein the gate comprises metal.

6. A field effect transistor (FET), comprising:

a semiconductor substrate;

source and drain regions having front surfaces defining a gate region between the source and drain regions on the semiconductor substrate;

a FET channel region coupled between the source and drain regions in the gate region, the FET channel region having a substantially circular cross-sectional shape, the FET channel region being trimmed to a desired dimension such that a front surface of the FET channel region is offset with respect to the front surfaces of the source and drain regions in a direction normal to the front surface of the source and drain regions; and

a protruding portion of the semiconductor substrate in the gate region beneath the FET channel region.