Electronic device including gate lines, bit lines, or a combination thereof

• US 7,642,594 B2
• Filed: 07/25/2005
• Issued: 01/05/2010
• Est. Priority Date: 07/25/2005
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Swift, Criag T., Ingersoll, Paul A., Chindalore, Gowrishankar L.
• Primary Examiner(s): Smith; Bradley K
• Assistant Examiner(s): Movva; Amar
• Application Number:
  US11/188,588
• Publication Number:
  US 20070018234A1
• Time in Patent Office: 1,625 Days
• Field of Search: 257/317, 257/E29.3
• US Class Current: 257/317
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/42352 with the gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An electronic device can include memory cells that are connected to gate lines, bit lines, or a combination thereof. In one embodiment, at least two sets of memory cells can be oriented substantially along a first direction, (e.g., rows or columns). A first gate line may be electrically connected to fewer rows or columns of memory cells as compared to a second gate line. For example, the first gate line may only be electrically connected to the first set of memory cells, and the second gate line may be electrically connected to the second and third sets of memory cells. In another embodiment, a first bit line may be electrically connected to fewer rows or columns of memory cells as compared to a second bit line. In still another embodiment, another set of memory cells may be oriented substantially along another direction that is substantially perpendicular to the first direction.

Claims

1. An electronic device comprising:

a trench within a substrate, wherein the trench has a first wall;

a first set of memory cells oriented substantially along a first direction;

a second set of memory cells oriented substantially along the first direction;

a first gate line electrically connected to the first set of memory cells, wherein the first gate line is a select gate line;

a second gate line electrically connected to the second set of memory cells, wherein;

when compared to the first gate line, the second gate line is electrically connected to more sets of memory cells that lie along the first direction;

the second gate line is a control gate line; and

within a memory array including the first and second sets of memory cells, a length of the first gate line is substantially parallel to a length of the second gate line; and

discontinuous storage elements, wherein for each memory cell within the first set of memory cells, a first set of the discontinuous storage elements lies between the second gate line and the first wall of the trench, wherein the first set of storage elements include a first storage element and a second storage element, both of which lie along the first wall, and wherein all of the first storage element lies at an elevation higher than all of the second storage element.

2. The electronic device of claim 1, wherein:

the first gate line is a select gate line, wherein at least a portion of the first gate line lies outside of the trench; and

the second gate line is a control gate line, wherein at least a portion of the second gate line lies within the trench.

3. The electronic device of claim 2, wherein:

each memory cell within the first and second sets of memory cells comprises a nonvolatile memory cell that includes a select gate electrode and a control gate electrode;

the first gate line is electrically connected to the select gate electrodes of the first set of memory cells; and

the second gate line is electrically connected to the control gate electrodes of the second set of memory cells.

4. The electronic device of claim 3, wherein:

discontinuous storage elements lie between channel regions and the control gate electrodes of the first and second sets of memory cells; and

substantially no discontinuous storage elements lie between channel regions and the select gate electrodes of the first and second sets of memory cells.

5. The electronic device of claim 1, wherein:

the trench includes a second wall spaced apart from the first wall;

a third set of memory cells includes memory cells within the second set of memory cells but does not include memory cells within the first set of memory cells; and

for each memory cell within the third set of memory cells, a second set of the discontinuous storage elements lies between the second gate line and the second wall of the trench.

6. The electronic device of claim 3, wherein:

the first gate line is electrically connected to one row or one column of memory cells; and

he second gate line is electrically connected to two rows or two columns of memory cells.

7. The electronic device of claim 1, further comprising a third set of memory cells oriented substantially along the first direction, wherein:

the first, second, and third sets of memory cells lie within different rows or different columns as compared to one another;

each memory cell within the third set of memory cells comprises a control gate electrode and a select gate electrode; and

the second gate line is electrically connected to the control gate electrodes of the second and third sets of memory cells.

8. The electronic device of claim 7, further comprising a first bit line, a second bit line, and a third bit line, wherein:

the first bit line is electrically connected to the first set of memory cells;

the second bit line is electrically connected to the second and third sets of memory cells; and

the third bit line is electrically connected to;

a first memory cell that is a part of the first set of memory cells but is not a part of the second set of memory cells; and

a second memory cell that is a part of the second set of memory cells but is not a part of the first set of memory cells.

9. The electronic device of claim 8, wherein:

the first and second bit lines are electrically connected to memory cells oriented substantially along the first direction; and

the third bit line is electrically connected to memory cells oriented substantially along a second direction that is substantially perpendicular to the first direction.

10. An electronic device comprising:

a trench within a substrate, wherein the trench has a first wall;

a first set of memory cells oriented substantially along a first direction;

a second set of memory cells oriented substantially along the first direction;

a first bit line electrically connected to the first set of memory cells, wherein the first bit line lies between two other bit lines;

a second bit line electrically connected to the second set of memory cells, wherein;

when compared to the first bit line, the second bit line is electrically connected to more sets of memory cells along the first direction; and

within a memory array including the first and second sets of memory cells, a length of the first bit line is substantially parallel to a length of the second bit line; and

discontinuous storage elements, wherein for each memory cell within the first set of memory cells, a first set of the discontinuous storage elements lies within the trench and adjacent to the first wall of the trench, wherein the first set of storage elements include a first storage element and a second storage element, both of which lie along the first wall, and wherein all of the first storage element lies at an elevation higher than all of the second storage element.

11. The electronic device of claim 10, wherein each memory cell within the first and second sets of memory cells comprises a nonvolatile memory cell that includes a select gate electrode and a control gate electrode.

12. The electronic device of claim 11, wherein:

discontinuous storage elements lie between channel regions and the control gate electrodes of the first and second sets of memory cells; and

substantially no discontinuous storage elements lie between channel regions and the select gate electrodes of the first and second sets of memory cells.

13. The electronic device of claim 10, wherein:

the trench includes a second wall spaced apart from the first wall;

a third set of memory cells includes memory cells within the second set of memory cells but does not include memory cells within the first set of memory cells; and

for each memory cell within the third set of memory cells, a second set of the discontinuous storage elements lies within the trench and adjacent to the second wall of the trench.

14. The electronic device of claim 10, further comprising a third set of memory cells, wherein:

the first, second, and third sets of memory cells lie within different rows or different columns as compared to one another;

the third set of memory cells is oriented substantially along the first direction; and

the second bit line is electrically connected to the third set of memory cells.

15. The electronic device of claim 10, wherein:

the first bit line is electrically connected to one row or one column of memory cells; and

the second bit line is electrically connected to two rows or two columns of memory cells.

16. The electronic device of claim 10, further comprising a first gate line, a second gate line, and a third gate line, wherein:

the first gate line is electrically connected to the first set of memory cells;

the second gate line is electrically connected to the second set of memory cells; and

the third gate line is electrically connected to;

a first memory cell that is a part of the first set of memory cells but is not a part of the second set of memory cells; and

a second memory cell that is a part of the second set of memory cells but is not a part of the first set of memory cells.

17. The electronic device of claim 16, wherein:

each of the first and second gate lines is a control gate line, wherein at least a part of the first gate line lies within the trench; and

the third gate line is a select gate line, wherein at least a part of the third gate line lies outside the trench.

18. The electronic device of claim 16, wherein:

the first and second gate lines are electrically connected to memory cells oriented substantially along the first direction; and

the third gate line is electrically connected to memory cells oriented substantially along a second direction that is substantially perpendicular to the first direction.

19. The electronic device of claim 18, wherein:

discontinuous storage elements lie between control gate electrodes and channel regions of the second and third sets of memory cells; and

substantially no discontinuous storage elements lie between select gate electrodes and channel regions of the first set of memory cells.