Power semiconductor device

• US 7,642,597 B2
• Filed: 11/13/2007
• Issued: 01/05/2010
• Est. Priority Date: 11/14/2006
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Saito, Wataru
• Primary Examiner(s): Tran; Long K
• Application Number:
  US11/939,050
• Publication Number:
  US 20080135930A1
• Time in Patent Office: 784 Days
• Field of Search: 257/287, 257/341, 257/401, 257/578, 257/E29.02, 257/E29.201, 257/E29.257, 257/E29.338, 257/498, 257/E29.016, 257/E29.136
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7812 with a substrate comprising an insulating layer, e.g. SOI-VDMOS transistors

Abstract

A power semiconductor device includes a semiconductor substrate having a plurality of trenches formed in an upper surface thereof; a buried insulating film; a buried field plate electrode; a control electrode; a first main electrode provided on a lower side of the semiconductor substrate; and a second main electrode provided on an upper side of the semiconductor substrate. The semiconductor substrate includes: a first semiconductor; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type; a fourth semiconductor layer; and a fifth semiconductor layer. The buried insulating film is thicker than a gate insulating film. At least one of the second semiconductor layer and the third semiconductor layer has a portion with its sheet dopant concentration varying along a depth direction of the semiconductor substrate.

Claims

1. A power semiconductor device comprising:

a semiconductor substrate having a plurality of trenches formed in an upper surface thereof;

a buried insulating film formed on an inner surface of the trenches;

a buried field plate electrode buried in the trenches;

a control electrode insulated from the semiconductor substrate by a gate insulating film;

a first main electrode provided on a lower side of the semiconductor substrate; and

a second main electrode provided on an upper side of the semiconductor substrate,

the semiconductor substrate including;

a first semiconductor layer of a first conductivity type with its lower surface connected to the first main electrode;

a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged parallel to the upper surface of the semiconductor substrate;

a fourth semiconductor layer of the second conductivity type formed above the second semiconductor layer and the third semiconductor layer and connected to the second main electrode; and

a fifth semiconductor layer of the first conductivity type selectively formed in an upper surface of the fourth semiconductor layer and connected to the second main electrode,

the buried insulating film being thicker than the gate insulating film,

at least one of the second semiconductor layer and the third semiconductor layer having a portion with its sheet dopant concentration varying along depth direction of the semiconductor substrate, the sheet dopant concentration in the third semiconductor layer being higher than the sheet dopant concentration in the second semiconductor layer in an upper part of the portion with varying sheet dopant concentration, and the sheet dopant concentration in the third semiconductor layer being lower than the sheet dopant concentration in the second semiconductor layer in a lower part of the portion.

2. The power semiconductor device according to claim 1, wherein the buried field plate electrode is connected to the control electrode.

3. The power semiconductor device according to claim 2, wherein the buried field plate electrode is integrally formed with the control electrode.

4. The power semiconductor device according to claim 1, wherein the trenches are shallower than the third semiconductor layer.

5. The power semiconductor device according to claim 4, wherein dopant concentration in the second semiconductor layer and the third semiconductor layer is relatively high in a region between the trenches and relatively low in a region below the trenches.

6. The power semiconductor device according to claim 4, wherein dopant concentration in a portion below the buried field plate electrode in the third semiconductor layer monotonically decreases downward from an upper end of the portion.

7. The power semiconductor device according to claim 5, wherein a slope of dopant concentration in a portion below the buried field plate electrode in the third semiconductor layer is smaller than a slope of dopant concentration in a portion between the buried field plate electrodes in the third semiconductor layer.

8. The power semiconductor device according to claim 4, further comprising a sixth semiconductor layer of the second conductivity type formed at a bottom of the trenches.

9. The power semiconductor device according to claim 1, wherein the buried field plate electrode, the second semiconductor layer and the third semiconductor layer are formed in a striped configuration, respectively.

10. The power semiconductor device according to claim 9, wherein as viewed from above, an extending direction of the second semiconductor layer and the third semiconductor layer is orthogonal to an extending direction of the buried field plate electrode.

11. The power semiconductor device according to claim 10, wherein an arrangement pitch of the buried field plate electrode is smaller than an arrangement pitch of the second semiconductor layer and the third semiconductor layer.

12. The power semiconductor device according to claim 1, further comprising a sixth semiconductor layer of the first conductivity type formed in a termination region and, and having a dopant concentration which is smaller than a dopant concentration in the second semiconductor layer,

the second semiconductor layer and the third semiconductor layer being not formed in the termination region.

13. The power semiconductor device according to claim 12, further comprising an seventh semiconductor layer of the second conductivity type formed in an upper surface of the seventh semiconductor layer.

14. The power semiconductor device according to claim 12, further comprising a field insulating film formed on the semiconductor substrate in the termination region, and a field plate electrode formed on the field insulating film and connected to the second main electrode or the control electrode.

15. The power semiconductor device according to claim 14, further comprising an seventh semiconductor layer of the second conductivity type formed in an upper surface of the seventh semiconductor layer.

16. The power semiconductor device according to claim 1, further comprising a sixth semiconductor layer of the first conductivity type formed between the first semiconductor layer and the second semiconductor layer and between the first semiconductor layer and the third semiconductor layer, and having a dopant concentration which is smaller than a dopant concentration in the second semiconductor layer.

17. A power semiconductor device comprising:

a semiconductor substrate having a plurality of trenches formed in an upper surface thereof;

a buried insulating film formed on an inner surface of the trenches;

a buried field plate electrode buried in the trenches;

a control electrode insulated from the semiconductor substrate by a gate insulating film;

a first main electrode provided on a lower side of the semiconductor substrate; and

a second main electrode provided on an upper side of the semiconductor substrate,

the semiconductor substrate including;

a first semiconductor layer of a first conductivity type with its lower surface connected to the first main electrode;

a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged parallel to the upper surface of the semiconductor substrate;

a fourth semiconductor layer of the second conductivity type formed above the second semiconductor layer and the third semiconductor layer and connected to the second main electrode; and

a fifth semiconductor layer of the first conductivity type selectively formed in an upper surface of the fourth semiconductor layer and connected to the second main electrode,

electric field strength in the second semiconductor layer and the third semiconductor layer along depth direction of the semiconductor substrate having a maximum value in a part other than an upper end and a lower end of the second semiconductor layer and the third semiconductor layer.

18. The power semiconductor device according to claim 17, wherein the electric field strength in the second semiconductor layer and the third semiconductor layer decreases from a center of the semiconductor substrate along a thickness direction toward upper and lower ends.

19. The power semiconductor device according to claim 18, wherein in an upper part of the second semiconductor layer and the third semiconductor layer, a sheet dopant concentration in the third semiconductor layer is higher than a sheet dopant concentration in the second semiconductor layer, and in a lower part of the second semiconductor layer and the third semiconductor layer, the sheet dopant concentration in the third semiconductor layer is lower than the sheet dopant concentration in the second semiconductor layer.

20. The power semiconductor device according to claim 18, wherein the buried insulating film has a portion whose thickness varies along the thickness direction of the semiconductor substrate, and the thickness of the buried insulating film increases downward in the portion.