Methods and apparatus for packaging integrated circuit devices

• US 7,642,629 B2
• Filed: 08/13/2007
• Issued: 01/05/2010
• Est. Priority Date: 06/16/2003
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Tessera Technologies Hungary Kft. (Adeia Inc.)
• Inventors: Katraro, Reuven, Aksenton, Julia, Zilber, Gil, Oganesian, Vage
• Primary Examiner(s): LEE, HSIEN MING
• Application Number:
  US11/891,867
• Publication Number:
  US 20080012115A1
• Time in Patent Office: 876 Days
• Field of Search: 257/678, 257/684, 257/690, 438106-109, 438/110, 438/113
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/02319 by using a preform
• CPC Class Codes: H01L 2224/02321 Reworking
• CPC Class Codes: H01L 2224/02335 Free-standing redistribution layers
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

Claims

1. A packaged chip, comprising:

a chip having a front surface, an active region at the front surface and a conductive pad at the front surface conductively connected to the active region;

a packaging layer having an inner surface confronting the active region of the chip, the packaging layer having an outer surface remote from the inner surface and a plurality of edge surfaces extending away from the outer surface,

wherein the conductive pad of the chip includes a projecting portion extending along the front surface of the chip beyond one of the edge surfaces of the packaging layer, the packaged chip includes an electrical conductor overlying the outer surface of the packaging layer and extending with the projecting portion of said conductive pad along the front surface in contact with the projecting portion of said conductive pad, and the inner surface of the packaging layer is spaced from at least a portion of the active region to define a gap.

2. A packaged chip as claimed in claim 1, wherein the electrical conductor extends along the one of the edge surfaces.

3. A packaged chip as claimed in claim 1, wherein the inner surface is defined by a recess in the packaging layer.

4. A packaged chip, comprising:

a chip having a front surface, an active region at the front surface and a conductive pad at the front surface conductively connected to the active region;

a packaging layer having an inner surface confronting the active region of the chip, the packaging layer having an outer surface remote from the inner surface and a plurality of edge surfaces extending away from the outer surface,

wherein the conductive pad of the chip includes a projecting portion extending along the front surface of the chip beyond one of the edge surfaces of the packaging layer, the packaged chip includes an electrical conductor overlying the outer surface of the packaging layer and extending with the projecting portion of said conductive pad along the front surface in contact with the projecting portion of said conductive pad, and the packaging layer consists essentially of semiconductor material.

5. A packaged chip as claimed in claim 4, further comprising insulation overlying the semiconductor material at the outer surface of the packaging layer, the electrical conductor overlying the insulation.

6. A packaged chip as claimed in claim 5, wherein the insulation includes a dielectric layer, the dielectric layer including at least one material selected from the group consisting of epoxy, silicon oxide, solder mask, silicon nitride, silicon oxynitride, polyimide, parylene, polynaphthalenes, fluorocarbons and acrylates.

7. A packaged chip, comprising:

a chip having a front surface, an active region at the front surface and a conductive pad at the front surface conductively connected to the active region;

a packaging layer having an inner surface confronting the active region of the chip, the packaging layer having an outer surface remote from the inner surface and a plurality of edge surfaces extending away from the outer surface,

wherein the conductive pad of the chip includes a projecting portion extending along the front surface of the chip beyond one of the edge surfaces of the packaging layer, the packaged chip includes an electrical conductor overlying the outer surface of the packaging layer and extending with the projecting portion of said conductive pad along the front surface in contact with the projecting portion of said conductive pad, the chip includes a plurality of the conductive pads having projecting portions extending beyond at least one of the plurality of edge surfaces and the packaged chip includes a plurality of the electrical conductors, the electrical conductors including conductive traces extending laterally along the projecting portions of the conductive pads along the at least one of the edge surfaces, the plurality of conductive pads extend from underneath the packaging layer to beyond the edge surfaces of the packaging layer, and the chip includes ledges exposed beyond the edge surfaces of the packaging layer and the plurality of conductive pads overlie the ledges.