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Methods and apparatus for packaging integrated circuit devices

  • US 7,642,629 B2
  • Filed: 08/13/2007
  • Issued: 01/05/2010
  • Est. Priority Date: 06/16/2003
  • Status: Expired due to Term
First Claim
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1. A packaged chip, comprising:

  • a chip having a front surface, an active region at the front surface and a conductive pad at the front surface conductively connected to the active region;

    a packaging layer having an inner surface confronting the active region of the chip, the packaging layer having an outer surface remote from the inner surface and a plurality of edge surfaces extending away from the outer surface,wherein the conductive pad of the chip includes a projecting portion extending along the front surface of the chip beyond one of the edge surfaces of the packaging layer, the packaged chip includes an electrical conductor overlying the outer surface of the packaging layer and extending with the projecting portion of said conductive pad along the front surface in contact with the projecting portion of said conductive pad, and the inner surface of the packaging layer is spaced from at least a portion of the active region to define a gap.

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