Stacked semiconductor package

• US 7,642,635 B2
• Filed: 09/12/2006
• Issued: 01/05/2010
• Est. Priority Date: 02/28/2003
• Status: Expired due to Fees

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Kikuchi, Wataru, Sugano, Toshio, Isa, Satoshi
• Primary Examiner(s): Lewis; Monica
• Application Number:
  US11/531,167
• Publication Number:
  US 20070001299A1
• Time in Patent Office: 1,211 Days
• Field of Search: 257/686, 257/697, 257/734, 257/737, 257/738, 257/773, 257/777, 257/778, 257/780, 257/786, 257/E23.085
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06579 TAB carriers; beam leads
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A stacked semiconductor package comprises two semiconductor chips (11, 12) each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern. The semiconductor chips are mounted on opposite surfaces of a substrate (13) so that the mounting surfaces are faced to each other through the substrate. The substrate is provided with a plurality of package pins formed in an area other than a chip mounting area and arranged in a pattern identical to the predetermined pattern. A pair of the corresponding chip pins of the semiconductor chips are connected to a via formed at an intermediate position therebetween by the use of branch wires equal in length to each other. The via is connected by a common wire to the package pin corresponding to the chip pins connected to the via.

Claims

1. A stacked semiconductor package comprising two semiconductor chips each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern, and a substrate having upper and lower surfaces on which the two semiconductor chips are mounted so that the mounting surfaces are faced to each other with the substrate interposed therebetween,

wherein the substrate has a plurality of package pins corresponding to the chip pins, respectively, said plurality of package pins being formed in an area which is different from a chip mounting area where either of the semiconductor chips is mounted and which becomes another lower surface when the substrate is folded in two to wrap the semiconductor chip mounted on the lower surface,

wherein at least one of the package pins is an option pin connected to a corresponding chip pin of either one of the semiconductor chips and at least one of the package pins is a regular pin connected to a corresponding chip pin of each of the semiconductor chips,

wherein the substrate has a common wire having one end connected to the regular pin and a branch wire portion connecting the other end of the common wire to two chip pins as the corresponding chip pins of the semiconductor chips;

and

wherein the branch wire portion includes a front layer side signal layer and a back layer side signal layer which are connected to the corresponding chip pins at points where wiring length from the one end of the common wire to one of the corresponding chip pins is substantially equal to that from the one end of the common wire to the other end of the corresponding chip pins.

2. A stacked semiconductor package according to claim 1, wherein:

the branch wire portion comprises a via formed in the vicinity of an intermediate position between the corresponding chip pins and connected to the other end of the common wire, and the front layer side signal layer and the back layer side signal layer which are substantially equal to each other in length and which connect the via to the corresponding chip pins.

3. A stacked semiconductor package according to claim 1, wherein the substrate is a multilayer substrate having a ground plane and/or a power supply plane, the common wire and the branch wire portion each forming a transmission line together with the ground plane and/or the power supply plane.

4. A stacked semiconductor package according to claim 3, wherein the transmission line comprises any one of a microstrip line, a strip line, and a parallel line.

5. A stacked semiconductor package according to claim 3, wherein the ground plane and/or the power supply plane includes a portion formed by a plurality of ground plane parts and/or power supply plane parts or a portion partially separated by a via or another wire.

6. A stacked semiconductor package according to claim 1, wherein each of the semiconductor chips is an elemental chip (bare die), a chip having a packaged structure obtained by mounting the elemental chip on a substrate, electrically connecting wires (pads) of the elemental chip and wires on the substrate by wire bonding, inner lead bonding, flip-chip connection, or the like, and encapsulating the chip and the substrate in a resin mold in order to protect a conductive pattern on the substrate, or a wafer level CSP or wafer process package.

7. A stacked semiconductor package according to claim 1, wherein the arrangement of the package pins is based on the predetermined pattern.

8. A stacked semiconductor package according to claim 7, wherein the package pins comprise pins arranged according to the predetermined pattern and additional pins.

9. A stacked semiconductor package according to claim 1, wherein the chip pins of one of the semiconductor chips are arranged on the substrate so as to be a mirror-image of the chip pins of the other of the semiconductor chips.

10. A stacked semiconductor package according to claim 1, wherein the two semiconductor chips are aligned with one another.

11. A stacked semiconductor package according to claim 1, wherein the chip pins of one of the semiconductor chips and the chip pins of the other of the semiconductor chips are aligned with one another.

12. A stacked semiconductor package according to claim 1, wherein the package pins are arranged in a pattern identical to the predetermined pattern.

13. A stacked semiconductor package according to claim 1, wherein the chip pins corresponding to the regular pin are in different relative locations on the semiconductor chips.