High-speed controller for phase-change memory peripheral device

• US 7,643,334 B1
• Filed: 08/09/2007
• Issued: 01/05/2010
• Est. Priority Date: 04/26/2007
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Ma, Abraham C., Lee, Edward W., Lee, Charles C.
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US11/836,264
• Time in Patent Office: 880 Days
• Field of Search: 365/163, 365/189.05, 365/230.03, 365/230.06, 365219-221
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell'"'"'s set-current pulse can be 100 ns, much longer than read or reset times. The write time depends on the write data state and is relatively long for set, but short for clear. A PCM chip has a lookup table (LUT) caching write data that is later written to a PCM bank. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the slower PCM. The PCM chip has upstream and downstream serial interfaces to other PCM chips arranged as a token stub. Requests are passed down the token-stub while acknowledgements are passed up the token-stub to the host'"'"'s memory controller. Shared chip-enable lines are driven by the upstream PCM chip for requests, and by the downstream PCM chip for acknowledgements.

Claims

1. A serializing token-stub phase-change memory (PCM) comprising:

an upstream serial interface to a memory controller or to an upstream phase-change memory device in a token-stub of phase-change memory devices;

a downstream serial interface to a downstream phase-change memory device in the token-stub of phase-change memory devices;

a deserializer that extracts a write address and a write word in a write request from a serial bitstream received by the upstream serial interface when the write address is within an address range of the serializing token-stub phase-change memory;

wherein the deserializer further extracts a read address in a read request from the serial bitstream received by the upstream serial interface when the read address is within the address range of the serializing token-stub phase-change memory;

a serializer that generates a serial output bitstream to the upstream serial interface from a read data word in response to the read request;

a host write buffer, coupled to the deserializer, for storing a write data word;

a host read buffer, coupled to the serializer, for storing the read data word;

a plurality of PCM cells each having a first logical state having an alloy in a crystalline phase and a second logical state having the alloy in an amorphous phase, wherein a resistance of the alloy is higher when in the amorphous phase than when in the crystalline phase;

a plurality of banks, each bank comprising;

an array of the plurality of PCM cells;

a row decoder, receiving a row portion of the write address or receiving a row portion of the read address, for selecting a row of the plurality of PCM cells selected by an activated word line selected from a plurality of word lines in the array;

a column decoder, receiving a column portion of the write address or receiving a column portion of the read address, for selecting a column of the plurality of PCM cells in the array as selected PCM cells;

local sense amplifiers for reading the read data word stored in the selected PCM cells in response to the read address; and

local write drivers activated by the write data word for driving a set pulse for a set period of time to the selected PCM cells that are being written to a first logical state, and for driving a reset pulse for a reset period of time to the selected PCM cells that are being written to a second logical state;

whereby set and reset pulses are driven to the selected PCM cells from the write data word received by the upstream serial interface.

2. The serializing token-stub phase-change memory of claim 1 further comprising:

an acknowledgement generator, coupled to the upstream serial interface, for generating an upstream acknowledgement signal in response to the read request;

a request generator, coupled to the downstream serial interface, for generating a downstream request signal in response to the read address or the write address not being within the address range;

an acknowledgement receiver, coupled to the downstream serial interface, for receiving an upstream acknowledgement signal indicating an acknowledgement bitstream to pass on to the upstream serial interface; and

a request receiver, coupled to the upstream serial interface, for receiving an upstream request signal indicating transmission of the serial bitstream containing the read request or the write request.

3. The serializing token-stub phase-change memory of claim 2 further comprising:

a cache for storing copies of data lines stored in the plurality of PCM cells, the cache having lines of data and tags of addresses for the lines of data;

write data lines coupled between the host write buffer and the cache, for initially storing the write data word in the cache; and

read data lines coupled between the host read buffer and the cache, for reading the read data word from the cache when a tag portion of the read address matches a tag in the cache,

whereby set and reset pulses are driven to the selected PCM cells from the write data word initially stored in the cache, freeing the write data lines for other data transfers when the set and reset pulses are applied.

4. The serializing token-stub phase-change memory of claim 3 further comprising:

a handshake protocol controller for delaying generation of the upstream acknowledgement signal by the upstream serial interface when the read data word is not stored in the cache,

whereby non-cached data delays generation of the upstream acknowledgement signal.

5. The serializing token-stub phase-change memory of claim 3 further comprising:

an upstream shared chip-enable line, coupled between the upstream serial interface and the upstream phase-change memory device in the token-stub, wherein the upstream serial interface drives the upstream shared chip-enable line when sending an acknowledgement serial bitstream; and

a downstream shared chip-enable line, coupled between the downstream serial interface and the downstream phase-change memory device in the token-stub, wherein the downstream serial interface drives the downstream shared chip-enable line when sending the serial bitstream.

6. The serializing token-stub phase-change memory of claim 3 wherein a PCM cell in the plurality of PCM cells comprises:

a select transistor receiving a word line on a gate, and having a channel between a bit line and a cell node;

an alloy resistor formed from the alloy, coupled between the cell node and an array voltage;

wherein the PCM cell has the first logical state when the alloy resistor has the alloy in the crystalline phase, the alloy resistor having a low resistance that increases a sensing current from the bit line through the select transistor;

wherein the PCM cell has the second logical state when the alloy resistor has the alloy in the amorphous phase, the alloy resistor having a high resistance that reduces the sensing current from the bit line through the select transistor;

wherein the high resistance is larger than the low resistance;

whereby the sensing current is altered by the alloy being in the crystalline phase and the amorphous phase.

7. The serializing token-stub phase-change memory of claim 6 wherein the alloy is a chalcogenide glass layer having a melting point that is higher than a crystallization point.

8. The serializing token-stub phase-change memory of claim 7 wherein the alloy is an alloy of germanium (Ge), antimony (Sb), and tellurium (Te).

9. A memory system comprising:

phase-change memory means for storing a data word as binary bits each represented by a chalcogenide glass layer having a melting point that is higher than a crystallization point, the chalcogenide glass layer forming a variable resistor that alters a sensing current when a binary bit is read;

wherein a crystalline state of the variable resistor represents a first binary logic state and an amorphous state of the variable resistor represents a second binary logic state for binary bits stored in the phase-change memory means;

upstream serial interface means for receiving a request from a host in response to a write request from the host, and for outputting an acknowledgement to the host in response to a read request from the host;

downstream serial interface means for sending the request from the host to a downstream phase-change-memory chip when the request contains an address that is not within an address range of the phase-change memory means, and for receiving a downstream acknowledgement to the host from the downstream phase-change-memory chip, and for passing the downstream acknowledgement to the upstream serial interface means for transmission toward the host;

de-serializing means for extracting a data I/O word from a serial bitstream containing the request received by the upstream serial interface means;

serializing means for generating an acknowledgement serial bitstream to the upstream serial interface means for transmission with the acknowledgement, the acknowledgement serial bitstream being generated from a data I/O word read from the phase-change memory means in response to a read request from the host; and

I/O buffer means for storing the data I/O word received from the host by the upstream serial interface means until a data word is accumulated,

whereby requests and acknowledgements are sent over upstream and downstream serial interfaces with data I/O words stored by the phase-change memory means.

10. The memory system of claim 9 wherein the phase-change memory means further comprises:

a plurality of bank means for storing data, each bank means comprising;

an array formed of a plurality of cells of the phase-change memory means, the array having rows and columns;

row decoder means, receiving a row address, for selecting a selected row of the plurality of cells in response to the row address;

column decoder means, receiving a column address, for selecting a selected column of the plurality of cells in response to the column address;

wherein selected cells of the phase-change memory means in the array are at an intersection of the selected row and the selected column;

bank write means for storing data bits to write into the selected cells;

sense amplifier means for reading data stored in the selected cells by sensing a difference in resistance of the variable resistor when in the crystalline state and when in the amorphous state;

multi-line page buffer means, coupled to the sense amplifier means and to the bank write means, for storing a plurality of lines of data for transfer with the phase-change memory means in the bank means;

lookup table means for storing tags and for storing lines of data I/O words received from the I/O buffer means, and for supplying data I/O words to the bus I/O means in response to the read request from the host that has a tag portion of a host address that matches a tag in the lookup table means;

data line transfer means, coupled between the I/O buffer means and lookup table means, for transferring the data word stored in the I/O buffer means to the lookup table means for storage; and

page transfer means, coupled between the lookup table means and the multi-line page buffer means, for transferring data lines stored in the lookup table means to the multi-line page buffer means for writing into the plurality of bank means;

whereby host write data is stored in the lookup table means before writing to the phase-change memory means in the bank means.

11. The memory system of claim 10 wherein each bank means further comprises:

set current timer means, coupled to the bank write means, for applying a set current for a set period of time to the selected cells to set variable resistors into the crystalline state when the binary bits being written are in the first binary logic state;

reset current timer means, coupled to the bank write means, for applying a reset current for a reset period of time to the selected cells to reset variable resistors into the amorphous state when the binary bits being written are in the second binary logic state;

wherein the reset current is at least twice the set current, and wherein the set current is at least twice a sensing current that passes through the variable resistor during a read operation;

wherein the set period of time is at least double the reset period of time,

whereby the variable resistor is set by a lower current for a longer time period, and reset by a higher current and a shorter time period.

12. The memory system of claim 11 further comprising:

error correction means, coupled to the lookup table means, for generating error-correction code for data I/O words stored in the lookup table means, and for checking and correcting errors in data I/O words read from the phase-change memory means and stored in the lookup table means using error-correction code stored in the phase-change memory means,

whereby error correction is performed for data in the lookup table means.

13. A serial token-interface phase-change memory device comprising:

an upstream serial interface that externally connects to a memory controller or to another serial token-interface phase-change memory device in a token-stub of serial token-interface phase-change memory devices that connect to the memory controller;

a downstream serial interface that externally connects to another serial token-interface phase-change memory device in the token-stub of serial token-interface phase-change memory devices;

a serial-parallel converter, coupled to the upstream serial interface, for generating a parallel bitstream from a serial bitstream received by the upstream serial interface, and for generating serial data for transmission by the upstream serial interface from a parallel read data word;

an address-data mux, coupled to the serial-parallel converter, for generating a parallel address and a parallel write data word from the parallel bitstream from the serial-parallel converter;

a plurality of banks of memory cells, each bank in the plurality of banks having an array of memory cells;

an alloy resistor in each memory cell in each array of memory cells, the alloy resistor storing binary data as solid phases each having a different resistivity;

wherein the alloy resistor changes from a crystalline state to an amorphous state when a memory cell is written from a logic 1 state to a logic 0 state in response to a reset current for a reset period of time;

wherein the alloy resistor changes from the amorphous state to the crystalline state when the memory cell is written from a logic 0 state to a logic 1 state in response to a set current for a set period of time;

wherein the amorphous state has a higher resistance than the crystalline state that is sensed by a sense amplifier;

a data input for receiving the parallel write data word from the address-data mux; and

a write input buffer, coupled to the data input to receive the parallel write data word,

wherein the parallel write data word converted from the serial bitstream is written to the alloy resistors in memory cells.

14. The serial token-interface phase-change memory device of claim 13 further comprising:

a lookup table for caching lines of the parallel write data words;

a tag table for storing tag portions of the parallel address for lines of the parallel write data words stored in the lookup table;

a multi-line page buffer, coupled to the plurality of banks of memory cells, for storing a page of data words for writing into the plurality of banks of memory cells or read from the plurality of banks of memory cells, wherein a page of data words comprises multiple lines of the parallel write data words or the parallel read data words; and

data lines coupled between the write input buffer, the lookup table, and the multi-line page buffer, for transferring data words,

whereby the parallel write data words are written into the lookup table for transfer to the multi-line page buffer for writing to the plurality of banks of memory cells.

15. The serial token-interface phase-change memory device of claim 14 further comprising:

a request input to the upstream serial interface for receiving a request signal that indicates transmission of the serial bitstream from the memory controller or to another serial token-interface phase-change memory device in the token-stub;

an acknowledgement output from the upstream serial interface for generating an acknowledgement signal to the memory controller or to another serial token-interface phase-change memory device in the token-stub after transmission of an acknowledgement serial bitstream by the upstream serial interface;

a request output from the downstream serial interface for generating a request signal to another serial token-interface phase-change memory device in the token-stub; and

an acknowledgement input to the downstream serial interface for receiving an acknowledgement signal that indicates transmission of the acknowledgement serial bitstream from another serial token-interface phase-change memory device in the token-stub.

16. The serial token-interface phase-change memory device of claim 15 further comprising:

an upstream shared chip-enable line, coupled between the upstream serial interface and the memory controller or another serial token-interface phase-change memory device in the token-stub, wherein the upstream serial interface drives the upstream shared chip-enable line when sending the acknowledgement serial bitstream; and

a downstream shared chip-enable line, coupled between the downstream serial interface and another serial token-interface phase-change memory device in the token-stub, wherein the downstream serial interface drives the downstream shared chip-enable line when sending the serial bitstream.

17. The serial token-interface phase-change memory device of claim 16 further comprising:

a plurality of bank write latches, coupled to the multi-line page buffer, wherein each bank in the plurality of banks has a local bank write latch that receives a bank portion of the data word from the data lines;

a plurality of write drivers, wherein each bank in the plurality of banks has a local write driver that applies the set current for the set period of time to memory cells being written by bits in the logic 1 state in the bank portion of the data word stored in the local bank write latches, and that applies the reset current for the reset period of time to memory cells being written by bits in the logic 0 state in the bank portion of the data word stored in the local bank write latches;

wherein the set period of time is at least 5 times longer than the reset period of time;

wherein unequal set and reset pulses are applied to the alloy resistors to for changes between the crystalline state and the amorphous state; and

a plurality of bank sense amplifiers, coupled to the multi-line page buffer, wherein each bank in the plurality of banks has a local bank sense amplifier that senses data stored in selected memory cells by sensing currents passing through alloy resistors having a higher resistance when in the amorphous state than when in the crystalline state;

wherein the bank portion of the data word is written from the local bank write latches into the memory cells while the data lines are disconnected from writing the local bank write latches, the data lines able to transfer data to other banks in the plurality of banks while the data word is written from the local bank write latches into the memory cells,

whereby concurrent writes and data transfers to different banks are performed.

18. The serial token-interface phase-change memory device of claim 13 wherein the data word stored in the memory cells is retained when power is disconnected,

wherein the alloy resistors remain in the amorphous state and remain in the crystalline state when power is disconnected;

whereby the data word is stored in non-volatile memory.

19. The serial token-interface phase-change memory device of claim 14 wherein the lookup table is a volatile memory, wherein lines of data words in the lookup table are lost when power is disconnected, while data words stored in the plurality of banks of memory cells are retained when power is disconnected,

whereby the data word is stored in non-volatile memory and cached in volatile memory.

20. The serial token-interface phase-change memory device of claim 14 wherein the lookup table comprises a smaller array of the memory cells each having the alloy resistor, the alloy resistor storing binary data as solid phases each having a different resistivity,

whereby the lookup table is non-volatile.