Method for erasing flash memory

• US 7,643,352 B2
• Filed: 06/03/2008
• Issued: 01/05/2010
• Est. Priority Date: 06/03/2008
• Status: Active Grant

• Current Assignee: Elite Semiconductor Memory Technology Inc.
• Original Assignee: Elite Semiconductor Memory Technology Inc.
• Inventors: Chen, Chung Zen
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US12/132,153
• Publication Number:
  US 20090296492A1
• Time in Patent Office: 581 Days
• Field of Search: 365/185.29, 365/185.22, 365/185.03
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing

Abstract

A method for erasing flash memory comprises the steps of: setting a critical ending condition; simultaneously erasing selected multiple sectors of the flash memory; stopping simultaneous erasing if one of the selected multiple sectors meets the critical ending condition; and erasing the remainder of each of the selected multiple sectors sequentially.

Claims

1. A method for erasing flash memory comprising the steps of:

setting a critical ending condition;

erasing selected multiple sectors of the flash memory simultaneously;

utilizing a first counter to track the number of erasing actions performed, wherein the first counter is used to indicate when to verify if one of the selected multiple sectors meets the critical ending condition;

utilizing a second counter to track the number of failures, wherein the second counter is used to indicate a time-out signal;

stopping simultaneous erasing if one of the selected multiple sectors meets the critical ending condition; and

erasing the remainder of each of the selected multiple sectors sequentially.

2. The method of claim 1, further comprising the step of resetting a flag which represents that the critical ending condition is met.

3. The method of claim 1, further comprising the step of recording the erasing status when the critical ending condition is met.

4. The method of claim 3, wherein the erasing status includes the voltage potential and the number of erasing actions performed.

5. The method of claim 1, wherein the critical ending condition is a passing rate of bits in the flash memory.

6. The method of claim 5, wherein if the first counter reaches a predetermined value, then all bits of one sector are verified to determine a passing rate.

7. A method for erasing flash memory comprising the steps of:

erasing selected multiple sectors of the flash memory simultaneously;

verifying bits of one sector upon a predetermined condition;

continually erasing selected multiple sectors of the flash memory simultaneously if the verification does not satisfy a critical ending condition;

utilizing a first counter to track the number of erasing actions performed, wherein the first counter is used to indicate the predetermined condition;

utilizing a second counter to track the number of failures, wherein the second counter is used to indicate a time-out signal;

stopping simultaneous erasing if the verification satisfies the critical ending condition; and

erasing the remainder of each of the selected multiple sectors sequentially if the verification satisfies the critical ending condition.

8. The method of claim 7, further comprising the step of resetting a flag which represents that the critical ending condition is met.

9. The method of claim 7, wherein the critical ending condition is a passing rate of bits in the flash memory.