Agile clock mechanism and method for ultrawide bandwidth communications system
First Claim
1. An ultra wide bandwidth timing generator, comprising:
- a high frequency clock generation circuit having low phase noise;
a low frequency control generation circuit; and
a modulation circuit coupled between the high frequency clock generation circuit and the low frequency control generation circuit,wherein the high frequency clock generation circuit generates a plurality of high frequency clock signals,the low frequency control generation circuit generates a plurality of low frequency control signals, andthe modulation circuit modulates the high frequency clock signals with the low frequency control signals to produce an agile timing signal at a predetermined frequency and phase by adjustments to at least one of frequency of the low frequency control signals, phase of the low frequency control signals, frequency of the high frequency clock signals, and phase of the high frequency clock signals,wherein the high frequency clock generation circuit is configured to receive at least one ofa coarse frequency control signal for coarse tuning of the agile timing signal in frequency, anda fast-modulation control signal for modulating the agile timing signal in frequency.
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Abstract
An ultra wide bandwidth communications system, method and computer program product including an ultra wide bandwidth timing generator. The timing generator includes a high frequency clock generation circuit having low phase noise; a low frequency control generation circuit; and a modulation circuit coupled between the high frequency clock generation circuit and the low frequency control generation circuit. The high frequency clock generation circuit generates a plurality of high frequency clock signals. The low frequency control generation circuit generates a plurality of low frequency control signals. The modulation circuit modulates the high frequency clock signals with the low frequency control signals to produce an agile timing signal at a predetermined frequency and phase. The agile timing signal is generated at the predetermined frequency and phase by adjustments to at least one of frequency of the low frequency control signals, phase of the low frequency control signals, frequency of the high frequency clock signals, and phase of the high frequency clock signals.
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Citations
19 Claims
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1. An ultra wide bandwidth timing generator, comprising:
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a high frequency clock generation circuit having low phase noise; a low frequency control generation circuit; and a modulation circuit coupled between the high frequency clock generation circuit and the low frequency control generation circuit, wherein the high frequency clock generation circuit generates a plurality of high frequency clock signals, the low frequency control generation circuit generates a plurality of low frequency control signals, and the modulation circuit modulates the high frequency clock signals with the low frequency control signals to produce an agile timing signal at a predetermined frequency and phase by adjustments to at least one of frequency of the low frequency control signals, phase of the low frequency control signals, frequency of the high frequency clock signals, and phase of the high frequency clock signals, wherein the high frequency clock generation circuit is configured to receive at least one of a coarse frequency control signal for coarse tuning of the agile timing signal in frequency, and a fast-modulation control signal for modulating the agile timing signal in frequency. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An ultra wide bandwidth timing generation method, comprising:
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generating a plurality of high frequency clock signals via a high frequency clock generation circuit having low phase noise; generating a plurality of low frequency control signals via a low frequency control generation circuit; modulating, via a modulation circuit coupled between the high frequency clock generation circuit and the low frequency control generation circuit, the high frequency clock signals with the low frequency control signals to produce an agile timing signal at a predetermined frequency and phase by adjustments to at least one of at least one of frequency of the low frequency control signals, phase of the low frequency control signals, frequency of the high frequency clock signals, and phase of the high frequency clock signals and at least one of the following steps; tuning of the agile timing signal in frequency based on a coarse frequency control signal received by the high frequency clock generation circuit, and modulating the agile timing signal in frequency based on a fast-modulation control signal received by the high frequency clock generation circuit. - View Dependent Claims (8, 9)
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10. An ultra wide bandwidth (UWB) communications receiver, comprising:
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a UWB demodulator configured to demodulate a UWB signal containing received data; a controller coupled to the UWB demodulator; and a UWB timing generator coupled to the controller and the UWB demodulator, the UWB timing generator configured to generate an agile timing signal provided to the demodulator, the UWB timing generator including; a high frequency clock generation circuit having low phase noise; a low frequency control generation circuit; and a modulation circuit coupled between the high frequency clock generation circuit and the low frequency control generation circuit, wherein the high frequency clock generation circuit generates a plurality of high frequency clock signals, the low frequency control generation circuit generates a plurality of low frequency control signals, and the modulation circuit modulates the high frequency clock signals with the low frequency control signals to produce the agile timing signal provided to the demodulator at a predetermined frequency and phase by adjustments to at least one of frequency of the low frequency control signals, phase of the low frequency control signals, frequency of the high frequency clock signals, and phase of the high frequency clock signals via the controller, wherein the high frequency clock generation circuit is configured to generate a first high frequency sinusoidal clock signal, a second high frequency sinusoidal clock signal and a third high frequency sinusoidal clock signal having approximately 0°
, 120° and
240°
phase relationships, respectively, such that the first through third high frequency sinusoidal clock signals can be positively weighted in the range of 0 to 1 and summed to produce the agile timing signal with any arbitrary phase.
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11. An ultra wide bandwidth timing generator, comprising:
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a high frequency clock generation circuit having low phase noise; a low frequency control generation circuit; a modulation circuit coupled between the high frequency clock generation circuit and the low frequency control generation circuit; and a phase-ramp control signal generation circuit configured to provide a phase-ramp control signal to the low frequency control generation circuit for fine tuning of the agile timing signal in frequency, wherein the high frequency clock generation circuit generates a plurality of high frequency clock signals, the low frequency control generation circuit generates a plurality of low frequency control signals, and the modulation circuit modulates the high frequency clock signals with the low frequency control signals to produce an agile timing signal at a predetermined frequency and phase by adjustments to at least one of frequency of the low frequency control signals, phase of the low frequency control signals, frequency of the high frequency clock signals, and phase of the high frequency clock signals, wherein the high frequency clock generation circuit is configured to receive at least one of a coarse frequency control signal for coarse tuning of the agile timing signal in frequency, and a fast-modulation control signal for modulating the agile timing signal in frequency. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification