Memory hub with internal cache and/or memory access prediction

• US 7,644,253 B2
• Filed: 11/01/2006
• Issued: 01/05/2010
• Est. Priority Date: 06/07/2002
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US11/592,041
• Publication Number:
  US 20070055817A1
• Time in Patent Office: 1,161 Days
• Field of Search: 711/154, 711/112, 711/137, 711/213, 711/114, 711/113, 710/22, 710/100, 710/3, 710/305, 709/104, 709/233, 709/229
• US Class Current: 711/213
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.

Claims

1. A memory hub, comprising:

a memory access device interface structured to interface with a memory access device; and

a plurality of memory interfaces coupled to the memory access device interface, the memory interfaces each structured to interface with respective memory devices, each of the memory interfaces comprising;

a memory controller;

a cache memory; and

a prediction unit structured to predict an address from which data are likely to be read based on an address from a prior memory access and, without receiving external command and address signals, to cause the memory controller in the respective memory interface to output signals indicative of a memory read operation from the predicted address.

2. The memory hub of claim 1 wherein the memory access device interface comprises a processor interface structured to interface with a processor.

3. The memory hub of claim 1 wherein the prediction unit is further structured to cause the memory interface to store in the cache memory read data received responsive to the signals indicative of a memory read operation.

4. The memory hub of claim 1 wherein the cache memory comprises dynamic random access memory.

5. The memory hub of claim 1 wherein each of the memory interfaces operates at the same clock speed.

6. A memory module, comprising:

a plurality of memory devices; and

a memory hub, the memory hub including a plurality of memory interfaces, the memory interfaces each structured to interface with the respective memory devices, each of the memory interfaces comprising;

a memory controller;

a cache memory; and

a prediction unit structured to predict an address from which data are likely to be read based on an address from a prior memory access and, without receiving external command and address signals, to cause the memory controller in the respective memory interface to read data from the predicted address and store the data in the cache memory.

7. The memory module of claim 6 wherein the memory hub comprises a processor interface structured to interface with a processor.

8. The memory module of claim 6 wherein the cache memory comprises dynamic random access memory.

9. The memory module of claim 6 wherein each of the memory interfaces operates at the same clock speed.

10. A computer system, comprising:

a processing unit operable to perform computing functions;

a system controller coupled to the processing unit;

at least one input device coupled to the processing unit through the system controller;

at least one output device coupled to the processing unit through the system controller;

at least one data storage devices coupled to the processing unit through the system controller;

a plurality of memory devices; and

a memory hub comprising;

a processor interface coupled to the processing unit;

a plurality of memory interfaces coupled the processor interface and to respective ones of the memory devices, each of the memory interfaces including a memory controller and a prediction unit structured to predict an address from which data are likely to be read based on an address from a prior memory access and, without receiving external command and address signals from the processing unit, to cause the memory controller in the respective memory interface to output data stored at the predicted address to the memory device to which the memory interface is coupled.

11. The computer system of claim 10, wherein the plurality of memory interfaces further comprise a cache and wherein the memory controller is structured to store the data read from the predicted address in the cache.

12. The computer system of claim 10 wherein the memory hub is physically included in the system controller.

13. The computer system of claim 10 wherein the plurality of memory devices are physically packaged in a memory module, and wherein the memory hub is physically included in the memory module.

14. The computer system of claim 10 wherein each of the memory interfaces operates at the same clock speed.

15. The computer system of claim 10 wherein each of the memory devices comprises a dynamic random access memory device.

16. A method of accessing a plurality of memory devices, comprising:

directing a first memory access request from a memory hub to a first memory device of a plurality of memory devices coupled to the memory hub;

predicting within the memory hub an address from which data are likely to be read from the first memory device based on an address from the first memory access request;

directing a second memory access request from the memory hub to a second of the plurality of memory devices without the memory hub receiving externally applied command and address signals;

performing a memory access operation in the second of the plurality of memory devices according to the second memory access request; and

while performing the memory access operation in the second of the plurality of memory devices, providing read data from the predicted address in the first memory device and storing the read data from the predicted address in a cache memory in the memory hub.

17. The method of claim 16 wherein the first memory access request on which the prediction was based comprises a read memory access.

18. The method of claim 16 wherein the memory access request on which the prediction was based comprises a write memory access.

19. The method of claim 16 further comprising:

directing a third memory request from the memory hub to the first memory device;

evaluating an address referenced by the memory request;

if the referenced address matches the predicted address, executing the memory access request on the read data stored from the predicted address stored in the cache memory.

20. The method of claim 16 wherein executing the memory access request on the read data comprises reading the read data from the cache memory.