Method and system for correcting soft errors in memory circuit

• US 7,644,341 B2
• Filed: 12/30/2004
• Issued: 01/05/2010
• Est. Priority Date: 12/30/2004
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Chien-Hua
• Primary Examiner(s): Lamarre; Guy J
• Assistant Examiner(s): Rizk; Sam
• Application Number:
  US11/026,354
• Publication Number:
  US 20060150062A1
• Time in Patent Office: 1,832 Days
• Field of Search: 714/763, 714/42, 711/104, 711/106, 711/167, 365/222
• US Class Current: 714/763
• CPC Class Codes: G01R 31/31816 Soft error testing; Soft error rate evaluation; Single event testing
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method and a system for correcting a soft error in a memory circuit operates during a stand-by mode. After reading data from at least one memory cell without outputting the read data through an input/output module of the memory circuit in the stand-by mode, it is determined whether the read data is a soft error. If so, a correct value is written to the memory cell if the read data is the soft error.

Claims

1. A method for correcting a soft error in a memory circuit during a stand-by mode, the method comprising the following steps performed during the stand-by mode:

performing an error correction routine comprising the steps of;

reading data from all memory cells in the memory circuit in a sequential manner without outputting the read data through an input/output module of the memory circuit;

determining whether the read data for each memory cell is a soft error; and

for each memory cells for which the read data is the soft error, writing a predetermined value to the memory cell,

wherein the reading or writing step of the error correction routine is stopped without completion thereof if the memory circuit is switched to normal operation mode out of stand-by mode for avoiding interfering with normal reading or writing operations.

2. The method of claim 1 wherein the reading is initiated on a periodical basis.

3. The method of claim 2 wherein a frequency for initiating the reading is adjustable depending on a frequency of soft error occurrence.

4. The method of claim 1 wherein the writing further comprises generating a flag signal to trigger a write access for writing the memory cell to correct the soft error.

5. The method of claim 1, further comprising the step of resuming said error correction routine from a point where it stopped after said normal operation mode upon returning to said stand-by mode.

6. The method of claim 1, further comprising the step of starting said error correction routine after said normal operation mode upon return to said stand-by mode.

7. The method of claim 1, wherein said memory cells are SRAM cells.

8. A method for correcting soft errors in a memory circuit, the method comprising:

generating an initiation signal for an error correction routine on a periodic basis when the memory circuit is in a stand-by mode;

during said stand-by mode reading one or more word values of a set of memory cells in response to the initiation signal without outputting the word values though an input/output module of the memory circuit; and

during said stand-by mode writing a correct value to the memory cell if any one of the word values is a soft error,

wherein a frequency for generating the initiation signal is adjustable depending on a frequency of soft error occurrence, and

wherein the error correction routine is deactivated or suspended without completion thereof if the memory circuit is switched to normal operation mode out of stand-by mode for avoiding interfering with normal reading or writing operations.

9. The method of claim 8 further comprising using an address counter for generating addresses of the memory cells for reading the word values thereof.

10. The method of claim 9 wherein the address counter generates the addresses sequentially.

11. The method of claim 8 wherein the writing further comprises generating a flag signal to trigger a write operation for writing the memory cell with the correct value if the word value is a soft error.

12. The method of claim 8 wherein the set of memory cells includes all memory cells in the memory circuit.

13. The method of claim 8, wherein said memory cells are SRAM cells.

14. A system for correcting soft errors of a memory circuit, the system comprising:

a timer for initiating a dummy read cycle of an error correction routine when the memory circuit is in a stand-by mode, wherein the timer generates a signal for initiating the dummy read cycle periodically and wherein a frequency for the timer to initiate the dummy read cycle is adjustable depending on a frequency of soft error occurrence;

an address counter for producing during said stand-by mode one or more addresses corresponding to one or more memory cells in the memory circuit after the dummy read cycle is initiated; and

an error checking and correcting circuit for reading one or more word values of one or more memory cells during said stand-by mode based on the addresses generated by the address counter and for writing a correct value to the memory cell during said stand-by mode if any of the word values is a soft error, wherein the error checking and correcting circuit is deactivated or suspended when a normal read or write operation is initiated such that the reading or writing is stopped without completion thereof for avoiding interfering with normal read or write operations.

15. The system of claim 14 wherein the address counter counts the addresses of the memory cells sequentially until all the memory cells in the memory circuit are examined.

16. The system of claim 14 wherein the error checking and correcting circuit generates a flag signal to trigger a write operation for writing the memory cell with the correct value if the word value is incorrect.

17. The system of claim 14, wherein said memory cells are SRAM cells.