Silent data corruption mitigation using error correction code with embedded signaling fault detection

• US 7,644,347 B2
• Filed: 09/30/2005
• Issued: 01/05/2010
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chittor, Suresh, Neefs, Henk, Cheng, Kai, Alexander, James W., Agarwal, Rajat, Brzezinski, Dennis W.
• Primary Examiner(s): Chaudry; M. Mujtaba K
• Assistant Examiner(s): Ahmed; Enam
• Application Number:
  US11/240,111
• Publication Number:
  US 20070089035A1
• Time in Patent Office: 1,558 Days
• Field of Search: 714/799
• US Class Current: 714/799
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for mitigating silent data corruption using an error correction code having embedded signaling fault detection. In an embodiment, a memory controller includes an extended error correction code (ECC) and link signaling fault detection logic. The extended ECC includes embedded signaling fault detection. In one embodiment, the extended ECC augments the signaling fault detection capabilities of the signaling fault detection logic.

Claims

1. An Apparatus comprising:

a first agent for coupling with a memory through a memory channel, the first agent to control link transmission on the memory channel;

a second agent coupled with the first agent, the second agent to implement an error correction code function and having embedded signaling fault detection logic; and

a third agent coupled with the first agent, the third agent including signaling fault detection logic, both the signaling fault detection logic and the embedded signaling fault detection logic to detect a signaling fault if a bit line failure condition does not exist, and, the embedded signaling fault detection logic but not the signaling fault detection logic to detect a signaling fault if a bit line failure condition does exist.

2. The apparatus of claim 1, wherein the embedded signaling fault detection logic includes an embedded implementation of a P-bit check code.

3. The apparatus of claim 2, wherein the P-bit check code includes a P-bit cyclic redundancy code.

4. The apparatus of claim 1, wherein the signaling fault detection logic of the third agent includes an implementation of an N-bit cyclic redundancy code.

5. The apparatus of claim 4, wherein P is greater than N.

6. The apparatus of claim 5, further comprising:

a bit-lane failure detection agent to detect a failure of a bit-lane in the memory channel.

7. The apparatus of claim 6, wherein the correction code is, at least in part, an implementation of a single b-bit error correcting-double bit error correcting (SbEC-DED) error correction code (ECC).

8. The apparatus of claim 1, wherein the memory channel is a fully buffered dual inline memory module (DIMM) channel.

9. The apparatus of claim, 8, wherein the fully buffered DIMM channel is a thirteen bit fully buffered DIMM channel.

10. The method comprising:

detecting that a bit line failure has not occurred;

applying first signaling fault detect logic and second signaling fault detection logic in response to said detecting;

detecting a signaling fault on a memory channel with the first signaling fault detection logic;

retrying a read operation for two consecutive reads in response to the detecting of the signaling fault;

determining if the retrying of the read operation resulted in identical data packets returned from the memory;

determining whether a data packet contains a memory content error; and

,

detecting that a bit line failure has occurred and disabling the first signaling fault detection logic in response thereto, wherein, the second signaling fault detection logic remains operative.

11. The method of claim 10, wherein the memory content error is one of a correctable error or an uncorrectable error and further comprising:

correcting the correctable error, if the data packet contains the correctable error; and

reporting the uncorrectable error, if the data packet contains an uncorrectable error.

12. The method of claim 10, wherein the first signaling fault detection logic includes an implementation of an N-bit cyclic redundancy code.

13. The method of claim 10, wherein after the applying and before the detecting the following is performed:

receiving a data packet from the memory channel;

performing an N-bit cyclic redundancy code (CRC) check on the packet with the first signaling fault detection logic; and

performing a P-bit CRC check on the packet with the second signaling fault detection logic.

14. The method of claim 13, wherein the N-bit CRC and the P-bit CRC are substantially performed in parallel.

15. A system comprising:

a memory channel;

a Memory module coupled with the memory channel, the memory module including one or more memory devices;

a memory controller coupled with the memory channel, the memory controller including a first agent to implement an error correction code function and having embedded signaling fault detection logic; and

the memory controller having a second agent having signaling fault detection logic, both the signaling fault detection logic and the embedded signaling fault detection logic to detect a signaling fault if a bit line failure condition does not exist, the embedded signaling fault detection logic but not the signaling fault detection logic to detect a signaling fault if a bit line failure condition does exist.

16. The system of claim 15, wherein

the signaling fault detection logic of the second agent includes an implementation of an N-bit cyclic redundancy code (CRC);

and

the embedded signaling fault detection logic includes an implementation of a P-bit error detection logic.

17. The system of claim 16, wherein the error correction code includes an implementation of a single b-bit error correcting double bit detecting (SbEC-DEC) error correction code (ECC).

18. The system of claim 15, wherein the memory channel is a fully buffered dual inline memory module (DIMM) memory channel.

19. The system of claim 18, wherein the fully buffered DIMM memory channel is a thirteen bit-lane fully buffered DIMM memory channel.