Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system

• US 7,645,710 B2
• Filed: 03/08/2007
• Issued: 01/12/2010
• Est. Priority Date: 03/09/2006
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Todorow, Valentin, Liu, Patricia M., Hung, Steven, Sato, Tatsuya, Chua, Thai Cheng, Olsen, Christopher Sean, Paterson, Alex M., Holland, John P.
• Primary Examiner(s): EVERHART, CARIDAD
• Application Number:
  US11/683,984
• Publication Number:
  US 20070212896A1
• Time in Patent Office: 1,041 Days
• Field of Search: 438/783, 438/784, 438/261, 257/E21.269, 257/E21.28, 257/E21.478, 257/491, 257/493, 257/639
• US Class Current: 438/783
• CPC Class Codes: H01J 37/32082 Radio frequency generated discharge H01J37/32357, H01J37/32366, H01J37/32394 and H01J37/32403 take precedence
• CPC Class Codes: H01J 37/32146 Amplitude modulation, includes pulsing
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/316 composed of oxides or glassy oxides or oxide based glass
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane

Abstract

The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material.

Claims

1. A method of forming a semiconductor device, comprising:

forming a dielectric layer having a desired thickness on a surface of a substrate;

disposing an amount of a first metal material within the dielectric layer to form a first concentration gradient through at least a portion of the thickness of the formed dielectric layer;

disposing an amount of a second metal material different than the first metal material within the dielectric layer to form a second concentration gradient through at least a portion of the thickness of the formed dielectric layer; and

depositing a third material over the dielectric layer, wherein the first material is disposed within the dielectric layer using a low energy sputtering process, wherein the low energy sputtering process comprises providing an RE energy at a first RE frequency and a first RF power to a processing region of a low energy sputtering chamber so that a first material of a target can be disposed within the dielectric layer.

2. The method of claim 1, further comprising annealing the substrate at a temperature between about 800°

C. and about 1100°

C.

3. The method of claim 1, wherein the thickness of the dielectric layer is less than about 40 Angstroms.

4. The method of claim 1, wherein the dielectric layer contains at least one material selected from a group consisting of silicon dioxide, hafnium oxide, zirconium oxide, hafnium silicate oxides, hafnium aluminate, hafnium lanthanum oxides, lanthanum oxides, and aluminum oxide.

5. The method of claim 1, wherein

the first material is hafnium and the concentration of the first material in the dielectric layer is less than about 30 atomic percent, and

the second material is lanthanum or aluminum that has a concentration less than about 10 atomic percent in the dielectric layer.

6. The method of claim 1, wherein the third material contains a material selected from a group consisting of polysilicon, tantalum, tantalum nitride, tantalum carbide, tantalum carbon nitride, tungsten, tungsten nitride, tantalum silicon nitride, hafnium, aluminum, platinum, ruthenium, cobalt, titanium, nickel, and titanium nitride.

7. The method of claim 1, wherein the low energy sputtering process comprises:

pulsing the RE energy delivered from the RF generator at the first frequency;

pulsing a DC voltage delivered to the target from a DC source assembly; and

synchronizing the pulsed RE energy and the pulsed DC voltage using a system controller.

8. The method of claim 1, further comprising exposing the surface of the substrate to an RF plasma comprising nitrogen prior to forming the dielectric layer.

9. The method of claim 1, wherein the first material and the second material are selected from a group consisting of aluminum, zirconium, titanium, hafnium, lanthanum, strontium, lead, yttrium, and barium.

10. The method of claim 9, further comprising exposing the dielectric layer, the first material, the second material, and the third material to an oxidizing environment, wherein the oxidizing environment using a thermal oxidation process or a plasma oxidation process.

11. A method of forming a semiconductor device, comprising:

forming a silicon containing dielectric layer having a desired thickness on a surface of a substrate;

forming a high-k dielectric layer having a desired thickness over the silicon containing dielectric layer;

disposing an amount of a first material within the high-k dielectric layer to form a concentration gradient through at least a portion of the thickness of the formed high-k dielectric layer, wherein the second material is selected from a group of materials comprising hafnium, lanthanum, aluminum, titanium, zirconium, strontium, lead, yttrium, and barium;

disposing an amount of a second material within the dielectric layer to form a second concentration gradient through at least a portion of the thickness of the formed high-k dielectric layer, wherein the second material is selected from a group of materials comprising hafnium, lanthanum, aluminum, titanium, zirconium, strontium, lead, yttrium, and barium; and

depositing a gate electrode material over the high-k dielectric layer, the first material, and the second material.

12. The method of claim 11, further comprising annealing the substrate at a temperature between about 800°

C. and about 1100°

C.

13. The method of claim 11, wherein the high-k dielectric layer contains a material selected from a group consisting of hafnium oxide, zirconium oxide, hafnium silicate oxides, hafnium aluminate, hafnium lanthanum oxides, lanthanum oxides, and aluminum oxide.

14. The method of claim 11, further comprising exposing the surface of the substrate or the formed silicon containing dielectric layer to an RE plasma comprising nitrogen.

15. The method of claim 11, wherein the combined thickness of the silicon containing dielectric layer and the high-k dielectric layer is less than about 40 Angstroms.

16. The method of claim 11, wherein the first material is hafnium and the concentration of the first material in the dielectric layer is less than about 30 atomic percent.

17. The method of claim 11, wherein the first material is lanthanum or hafnium that has a concentration less than about 10 atomic percent or the second material is aluminum that has a concentration less than about 10 atomic percent.

18. The method of claim 11, further comprising exposing the first material and the second material to an oxidizing environment, wherein the oxidizing environment using a thermal oxidation process or a plasma oxidation process.

19. The method of claim 11, wherein the gate electrode material contains a material selected from a group consisting of polysilicon, tantalum, tantalum nitride, tantalum carbon nitride, tantalum carbide, tungsten, tungsten nitride, tantalum silicon nitride, hafnium, aluminum, platinum, ruthenium, cobalt, titanium, nickel, and titanium nitride.