Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit

• US 7,646,068 B2
• Filed: 07/10/2006
• Issued: 01/12/2010
• Est. Priority Date: 08/15/2003
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ko, Chih-Hsin, Yeo, Yee-Chia, Lee, Wen-Chin, Hu, Chenming, Lin, Chun-Chieh
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US11/483,913
• Publication Number:
  US 20060255365A1
• Time in Patent Office: 1,282 Days
• Field of Search: 257/350, 257/379, 257/536, 257/537, 257/E21.431, 257/E21.438, 257/E27.016, 438/200, 438/210
• US Class Current: 257/379
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

Claims

1. A semiconductor chip comprising:

a semiconductor substrate;

a first active region disposed in the substrate;

a second active region disposed in the substrate;

a resistor formed in the first active region, the resistor including a doped region formed between two terminals;

a strained channel transistor formed in the second active region, the strained channel transistor including first and second stressors formed in the substrate oppositely adjacent a strained channel region, wherein the first and second stressors extend into the substrate from a surface of the substrate; and

a layer over the resistor and the strained channel transistor, the layer in contact wth the resistor.

2. The semiconductor chip of claim 1, wherein the doped region has a doping type that is opposite to a doping type of a portion of the semiconductor substrate underlying the doped region.

3. The semiconductor chip of claim 1, wherein the doped region has a doping concentration in the range of about 10¹⁶ to about 10¹⁹ cm⁻

3.

4. The semiconductor chip of claim 1, wherein the doped region has an n-type doping.

5. The semiconductor chip of claim 1, wherein the doped region has a p-type doping.

6. The semiconductor chip of claim 1, wherein the semiconductor substrate comprises a semiconductor-on-insulator substrate.

7. A semiconductor chip comprising:

a semiconductor substrate;

a first active region disposed in the substrate;

a second active region disposed in the substrate;

a resistor formed in the first active region, the resistor including a doped region formed between two terminals; and

strained channel transistor formed in the second active region, the strained channel transistor including a gate dielectric and a strained channel region having a first lattice constant and first and second stressors having a second lattice constant that is different from the first lattice constant formed in the substrate oppositely adjacent the strained channel region and adjacent to a major surface of the semiconductor substrate, the major surface of the semiconductor substrate in contact with the gate dielectric; and

a contact etch stop layer over the resistor and the strained channel transistor, the contact etch stop layer sharing an interface with the resistor.

8. The semiconductor chip of claim 7, wherein the second lattice constant is larger than the first lattice constant.

9. The semiconductor chip of claim 7, wherein the first strained channel region comprises silicon and the first and second stressors comprise silicon and germanium.

10. The semiconductor chip of claim 9, wherein the strained channel transistor is a p-channel transistor.

11. The semiconductor chip of claim 7, wherein the second lattice constant is smaller than the first lattice constant.

12. The semiconductor chip of claim 7, wherein the strained channel region is silicon and the first and second stressors comprise silicon and carbon.

13. The semiconductor chip of claim 12, wherein the strained channel transistor is an n-channel transistor.

14. The semiconductor chip of claim 7, wherein the doped region has a doping type that is opposite to a doping type of a portion of the semiconductor substrate underlying the doped region.

15. The semiconductor chip of claim 7, wherein the doped region has a doping concentration in the range of about 10¹⁶ to about 10¹⁹ cm⁻

3.

16. The semiconductor chip of claim 7, wherein the doped region has an n-type doping.

17. The semiconductor chip of claim 7, wherein the doped region has a p-type doping.

18. A semiconductor chip comprising:

a semiconductor substrate;

a first active region disposed in the substrate;

a second active region disposed in the substrate;

a resistor formed in the first active region, the resistor including a doped region formed between two terminals; and

a strained channel transistor formed in the second active region, the strained channel transistor including a gate stack comprising a gate dielectric and a gate electrode, spacers formed oppositely adjacent the gate stack, and first and second stressors formed in the substrate oppositely adjacent a strained channel region, the first and second stressors extending at least to a major surface of the substrate, the major surface of the substrate sharing an interface with the gate dielectric;

wherein a surface of the substrate in the first active region is substantially clear of the gate dielectric.

19. The semiconductor chip of claim 18, wherein the gate dielectric comprises a high permittivity dielectric selected from the group consisting of aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium silicate, zirconium oxide, zirconium oxynitride, zirconium silicate, yttrium oxide, lanthanum oxide, cerium oxide, titanium oxide, tantalum oxide, and combinations thereof.

20. The semiconductor chip of claim 18, wherein the gate electrode comprises a material selected from the group consisting of poly-crystalline silicon, poly-crystalline silicon-germanium, a metal, a metallic nitride, a metallic silicide, a metallic oxide, and combinations thereof.