Level shifting circuit having junction field effect transistors

• US 7,646,233 B2
• Filed: 07/28/2006
• Issued: 01/12/2010
• Est. Priority Date: 05/11/2006
• Status: Expired due to Fees

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: SuVolta, Inc.
• Inventors: Thummalapally, Damodar R., Chou, Richard K.
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US11/495,908
• Publication Number:
  US 20070262806A1
• Time in Patent Office: 1,264 Days
• Field of Search: 327/306, 327/307, 327534-537, 327/333
• US Class Current: 327/536
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A level shifting circuit can include a first driver junction field effect transistor (JFET) having a source coupled to a reference supply node and a second driver JFET of a second conductivity type having a source coupled to a boosted supply node, and a first charge pump circuit. The first charge pump circuit can be coupled between the first driver control node and an input node coupled to receive an input signal, and can couple a first terminal of a first capacitor between a reference supply node and a power supply node in response to an input signal. The power supply node can be coupled to receive a power supply potential, the reference supply node can be coupled to receive a reference potential, and the boosted power supply node can be coupled to receive a boosted potential. The reference potential can be between the power supply potential and the boosted potential.

Claims

1. A level shifting circuit, comprising:

a first driver p-type junction field effect transistor (JFET) of a having a source coupled to a reference supply node, a drain coupled to an output node, and a gate coupled to a first driver control node;

a second driver n-type JFET having a source coupled to a boosted supply node and a drain coupled to the output node; and

a first charge pump circuit coupled between the first driver control node and an input node coupled to receive an input signal, the first charge pump circuit coupling a first terminal of a first capacitor between the reference supply node and a power supply node in response to the input signal;

wherein

the power supply node is coupled to receive a power supply potential, the reference supply node is coupled to receive a reference potential, the boosted power supply node is coupled to receive a boosted potential, the power supply potential is positive with respect to the reference potential, and the boosted potential is negative with respect to the reference potential.

2. The level shifting circuit of claim 1, wherein:

the first driver p-type JFET and second driver n-type JFET are both four terminal JFETs having a first control gate separated from a second control gate by a channel region.

3. The level shifting circuit of claim 1, further including:

the second driver n-type JFET includes a gate coupled to a second driver control node; and

a second charge pump circuit coupled to the input node that couples a first terminal of a second capacitor between the reference supply node and the power supply node in response to the input signal.

4. The level shifting circuit of claim 3, wherein:

the second charge pump circuit includes

a pump JFET having a gate coupled to the first terminal of the second capacitor, a drain coupled to a second terminal of the second capacitor, and a source coupled to the reference supply node, and

a control JFET having a source coupled to the reference supply node, a drain coupled to the second driver control node, and a gate coupled to the second terminal of the second capacitor.

5. The level shifting circuit of claim 3, further including:

a logic circuit coupled between the input node and the second charge pump circuit that inverts the input signal with respect to the input signal received by the first charge pump circuit.

6. The level shifting circuit of claim 3, further including:

a second driver clamp circuit coupled between the output node and the second charge pump circuit that clamps a second terminal of the second capacitor to a predetermined level below the reference potential when the second driver n-type JFET provides a low impedance path between the boosted power supply node and the output node.

7. The level shifting circuit of claim 1, wherein:

the first charge pump circuit further includes a pump JFET having a gate coupled to the first terminal of the first capacitor, a drain coupled to a second terminal of the first capacitor and to the first driver control node, and a source coupled to the reference supply node.

8. The level shifting circuit of claim 1, further including:

an enable n-type JFET having a source coupled to the drain of the second driver n-type JFET, a gate coupled to the first driver control node, and a drain coupled to the output node.

9. The level shifting circuit of claim 1, further including:

a first driver clamp circuit coupled between the boosted power supply node and the first charge pump circuit that clamps a second terminal of the first capacitor to a predetermined level below the boosted potential when first driver p-type JFET provides a low impedance path between the reference power supply node and the output node.

10. A level shifting circuit, comprising:

a first charge pump circuit comprising at least a first pump junction field effect transistor (JFET) having a source-drain path coupled between a reference supply node and a first driver control node and a first capacitor coupled to the first driver control node;

a second charge pump circuit comprising at least a second pump JFET having a source-drain path coupled between the reference supply node and a second driver control node, and a second capacitor coupled to the gate of the second pump JFET; and

a driver section that selectively couples an output node between the reference supply node and a boosted supply node in response to a first driver control node potential and a second driver control node-potential.

11. The level shifting circuit of claim 10, wherein:

the first pump JFET comprises an n-channel JFET; and

the second pump JFET comprises a p-channel JFET.

12. The level shifting circuit of claim 10, wherein:

the second charge pump circuit further includes a third pump JFET having a source-drain path coupled between the gate of the second pump JFET and the reference supply node.

13. The level shifting circuit of claim 10, further including:

a feedback path coupled between the second driver control node and the boosted supply node that provides a low or high impedance path according to the potential at the output node.

14. The level shifting circuit of claim 10, further including:

the first capacitor has a first terminal coupled to a first charge pump input node and a second terminal coupled to the first driver control node;

the second capacitor has a first terminal coupled to a second charge pump input node and a second terminal coupled to the second driver control node; and

an input driver circuit that selectively couples the first charge pump input node and second charge pump input nodes between the reference supply node and a power supply node;

wherein

the power supply node is coupled to receive a power supply voltage having a first polarity with respect to the reference supply node, and the boosted supply node is coupled to receive a boosted supply voltage having a second polarity with respect to the reference supply node.

15. The level shifting circuit of claim 10, wherein:

the driver section comprises

at least a first driver JFET of a first conductivity type having a source-drain path coupled between the reference supply node and the output node and a gate coupled to the first driver control node, and

at least a second driver JFET of a second conductivity type having a source-drain path coupled between the output node and the boosted supply node, and a gate coupled to the second driver control node.

16. A level shifting circuit, comprising:

a driver section that includes

a first driver junction field effect transistor (JFET) having a source-drain path coupled between a reference supply node and an output node, and

a second driver JFET having a source-drain path coupled between the output node and a boosted supply node; and

a variable threshold JFET circuit, coupled between the reference supply node and a power supply node, comprising a plurality of variable threshold JFETs, each variable threshold JFET having two control gates with at least one control gate being coupled to the output node;

wherein

the power supply node is coupled to receive a power supply voltage that has a first polarity with respect to the reference voltage, and the boosted supply node is coupled to receive a boosted supply voltage that has a second polarity with respect to the reference voltage.

17. The level shifting circuit of claim 16, further including:

a first charge pump circuit comprising a first capacitor coupled between the first driver control node and a first charge pump input node;

a second charge pump circuit comprising a second capacitor coupled to a second charge pump input node; and

an input circuit coupled between the power supply node and the reference supply node that selectively couples the first and second charge pump input nodes to either the power supply node or the reference supply node according to an input signal.

18. The level shifting circuit of claim 17, wherein:

the input circuit comprises

at least a first input JFET of a first conductivity type having a source-drain path coupled between the power supply node and the first charge pump input node and a gate coupled to an input node,

at least a second input JFET of a second conductivity type having a source-drain path coupled between the reference supply node and the first charge pump input node and a gate coupled to the input node,

at least a third input JFET of the first conductivity type having a source-drain path coupled between the power supply node and the second charge pump input node and a gate coupled to the input node, and

at least a fourth input JFET of the second conductivity type having a source-drain path coupled between the reference supply node and the second charge pump input node and a gate coupled to the input node.