Integrated circuit for setting a memory cell based on a reset current distribution
First Claim
Patent Images
1. An integrated circuit comprising:
- an array of resistance changing memory cells; and
a first circuit configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell, the pulse based on a reset current distribution for the array of memory cells.
3 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current distribution for the array of memory cells.
28 Citations
23 Claims
-
1. An integrated circuit comprising:
-
an array of resistance changing memory cells; and a first circuit configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell, the pulse based on a reset current distribution for the array of memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A system comprising:
-
a host; and a memory device communicatively coupled to the host, the memory device comprising; an array of phase change memory cells; and a write circuit configured to set a selected memory cell to a crystalline state by applying a set pulse to the selected memory cell, the set pulse based on a reset current distribution for the array of memory cells. - View Dependent Claims (10, 11, 12, 13)
-
-
14. A system comprising:
-
a test circuit; and a memory device communicatively coupled to the test circuit, the memory device comprising; an array of resistance changing memory cells; and a configuration device for defining a set pulse; wherein the test circuit is configured to determine a reset current distribution for the array of memory cells and program the configuration device to define the set pulse based on the reset current distribution. - View Dependent Claims (15, 16, 17, 18)
-
-
19. A method for programming a memory, the method comprising:
-
determining a reset current distribution for an array of resistance changing memory cells; dividing the reset current distribution into at least two segments; determining a set pulse amplitude for each segment; and combining the set pulse amplitudes into a decreasing stair step pulse. - View Dependent Claims (20, 21, 22, 23)
-
Specification