Non-volatile memory with dynamic multi-mode operation

• US 7,646,636 B2
• Filed: 07/27/2007
• Issued: 01/12/2010
• Est. Priority Date: 02/16/2007
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US11/829,410
• Publication Number:
  US 20080198651A1
• Time in Patent Office: 900 Days
• Field of Search: 365/185.03, 365/185.01, 365/185.12, 365/185.33, 365/168, 365/185.11
• US Class Current: 365/185.03
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5646 Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"

Abstract

A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device.

Claims

1. A flash memory device comprising:

a NAND flash memory array having a memory block with a first page for storing multiple bit per cell (MBC) data;

a command decoder for issuing one of an MBC program command and a single bit per cell (SBC) program command in response to an external program command;

a control logic circuit for executing a programming algorithm in response to either the MBC program command or the SBC program command; and

,

flash memory circuitry for programming, in response to the programming algorithm, a second page in the memory block of the NAND flash memory array to store SBC data.

2. The flash memory device of claim 1, wherein the command decoder includes an SBC command decoder for issuing the SBC program command, and an MBC command decoder for issuing the MBC program command.

3. The flash memory device of claim 1, wherein the memory array includes first subdivisions configured for storing data in an MBC storage mode in response to the MBC program command, and second subdivisions configured for storing data in an SBC storage mode in response to the SBC program command.

4. The flash memory device of claim 3, wherein the first subdivisions and the second subdivisions include groups of memory pages.

5. The flash memory device of claim 3, wherein each subdivision is associated with a mode tag for designating the MBC storage mode or the SBC storage mode.

6. A method for storing data in a NAND flash memory device comprising:

a) powering up the NAND flash memory device to have at least one subdivision configured in a first storage mode or a second storage mode;

b) executing internal flash operations in response to commands after the NAND flash memory device is powered up;

d) converting the at least one subdivision from the first storage mode to the second storage mode in response to a specific command of the commands; and

e) programming the data to a first subdivision configured in the first storage mode or a second subdivision configured in the second storage mode in response to a program command.

7. The method of claim 6, wherein the first storage mode is a multiple bit per cell (MBC) storage mode and the second storage mode is a single bit per cell (SBC) storage mode.

8. The method of claim 7, wherein converting is executed in response to a predetermined criteria.

9. The method of claim 8, wherein the predetermined criteria is an MBC program erase limit.

10. The method of claim 9, wherein converting includes comparing a program/erase counter corresponding to the first subdivision with the MBC program/erase limit.

11. The method of claim 10, wherein programming includes programming the data to the first subdivision if the program/erase counter is less than the predetermined MBC program/erase limit, and programming the data to the second subdivision if the program/erase counter is at least the predetermined MBC program/erase limit.

12. The method of claim 11, wherein programming further includes erasing the first subdivision if the data is programmed to the second subdivision.

13. The method of claim 11, wherein programming further includes setting the mode tag corresponding to the first subdivision to a state indicative of the second storage mode.

14. The method of claim 11, wherein programming further includes resetting the program/erase counter.

15. The method of claim 8, wherein the predetermined criteria is a specific profile of the data.

16. The method of claim 15, wherein the specific profile of the data includes a set of data file types.

17. The method of claim 16, wherein programming includes programming the data to the first subdivision if the data has a profile matching the specific profile, and programming the data to the second subdivision if the profile mismatches the specific profile.

18. The method of claim 6, wherein the first subdivision includes a block, the block having a predetermined number of pages.

19. The method of claim 6, wherein the first subdivision includes a page, and a predetermined number of the pages are included in a block.

20. The method of claim 6, wherein the first storage mode is a single bit per cell (SBC) storage mode and the second storage mode is a multiple bit per cell (MBC) storage mode.

21. The method of claim 20, wherein converting includes comparing an SBC program/erase counter corresponding to the first subdivision to a reclaim limit, and checking a state of a lock bit corresponding to the first subdivision if the program/erase counter is less than the reclaim limit.

22. The method of claim 21, wherein converting further includes changing a state of a mode tag corresponding to the first subdivision if the state of the lock bit is false.

23. The method of claim 22, wherein converting further includes setting the lock bit to true after the state of the mode tag is changed.

24. The method of claim 6, wherein the specific command includes a programming command.

25. A method for selectively programming data in a NAND flash memory device in one of a multiple bit per cell (MBC) storage mode and a single bit per cell (SBC) storage mode, comprising:

a) receiving data;

b) determining a high reliability level or a low reliability level of the data;

c) programming the data in the SBC storage mode to SBC subdivisions if the data is determined to be high reliability;

d) programming the data in the MBC storage mode to MBC subdivisions if the data is determined to be low reliability; and

,

e) converting any number of the MBC subdivisions to the SBC storage mode or any number of the SBC subdivisions to the MBC storage mode.

26. The method for selectively programming data of claim 25, wherein converting includes programming storage mode data identifying the SBC subdivisions and the MBC subdivisions to the NAND flash memory device.

27. The method for selectively programming data of claim 26, further including preventing conversion of an SBC subdivision to the MBC storage mode.

28. The method for selectively programming data of claim 27, wherein preventing conversion includes programming locking data for preventing programming of the storage mode data.

29. A method for reading data from a NAND flash memory block having a multiple bit per cell (MBC) page and a single bit per cell (SBC) page, comprising:

a) receiving a read address for reading the MBC page or the SBC page of the NAND flash memory block;

b) executing an MBC read operation at the read address if a mode tag corresponding to the MBC page has a first logic state; and

,

c) executing an SBC read operation at the read address if the mode tag corresponding to the SBC page has a second logic state.

30. The method for reading data of claim 29, including initializing an address mapping table with mode tags corresponding to each page of the flash memory array prior to receiving the read address.

31. The method for reading data of claim 30, wherein initializing includes

powering up the flash memory array,

reading the mode tags stored in each page of the flash memory array, and

storing the mode tags with logical address entries corresponding to each page of the flash memory array.

32. The method for reading data of claim 31, wherein reading the mode tags includes executing an SBC read operation for reading the mode tags in each page of the flash memory array.

33. The method for reading data of claim 29, wherein receiving includes issuing an external read command from a flash controller to a flash memory device, the external read command being generated in response to the read address and the logic state of the mode tag corresponding to the read address.

34. The method for reading data of claim 33, wherein executing the MBC read operation includes decoding the external read command within the flash memory device and issuing one of an internal MBC read command and an internal SBC read command.

35. A method for programming data in a subdivision of a NAND flash memory device, comprising:

programming the data to the subdivision in a first storage mode;

monitoring program/erase cycles of the subdivision; and

,

converting the subdivision to a second storage mode if the program/erase cycles of the subdivision reaches a predetermined limit.

36. The method of claim 35, wherein the subdivision is a first subdivision and converting includes programming the data stored in the first subdivision to a second subdivision in the first storage mode.

37. The method of claim 36, wherein converting further includes changing storage mode data corresponding to the first subdivision for identifying the second storage mode of the first subdivision.

38. The method of claim 37, wherein the storage mode data includes a mode tag bit stored in an address mapping table for identifying the second storage mode of the subdivision.

39. The method of claim 37, wherein changing includes programming a bit in a tag bit field of the first subdivision for identifying the second storage mode of the first subdivision.

40. The method of claim 36, wherein the first storage mode is a multiple bit per cell (MBC) storage mode, and the second storage mode is a single bit per cell (SBC) storage mode.

41. The method of claim 35, wherein the first storage mode is a single bit per cell (SBC) storage mode, and the second storage mode is a multiple bit per cell (MBC) storage mode.

42. The method of claim 35, wherein the subdivision includes a memory block.

43. The method of claim 35, wherein the subdivision includes a page of a memory block.

44. The method of claim 35, wherein programming includes incrementing a counter corresponding to the program/erase cycles of the subdivision when the data is programmed to the subdivision.

45. The method of claim 35, wherein a counter corresponding to the program/erase cycles of the subdivision is reset after converting.