Memory device with programmable receivers to improve performance

• US 7,646,649 B2
• Filed: 11/18/2003
• Issued: 01/12/2010
• Est. Priority Date: 11/18/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Hazelzet, Bruce G., Kellogg, Mark W., Rankin, Darcie J.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/707,053
• Publication Number:
  US 20050108468A1
• Time in Patent Office: 2,247 Days
• Field of Search: 365/189.05, 365/226, 365/233.55
• US Class Current: 365/189.05
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits

Abstract

A memory system having a plurality of DRAMs which are selectively provided non-inverted or inverted signals. The DRAMs have the ability to accept non-inverted or inverted address/command signals from a register that drives a plurality of signals simultaneously. The system includes DRAM receivers with programmable input polarity and a register with programmable output polarity.

Claims

1. A memory system comprising:

a plurality of DRAMs having circuits to accept non-inverted input signals and inverted input signals;

a register programmed to provide inverted and non-inverted signals to the DRAMs; and

programmable pins in the register and the DRAMs to enable operation in either non-inverted or inverted mode, wherein a first programmable pin is connected to ground to enable an inverting mode and a second programmable pin is connected to Vdd to operate in a non-inverting mode.

2. The memory system of claim 1 which indicates re-drive circuitry, which can output both non-inverted and inverted polarity signals from one or more input signals.

3. The memory system of claim 1 wherein the DRAMs are mounted on a DIMM.

4. A memory system of claim 1 in which the register drives either non-inverted or inverted signals to the DRAMs using a programmable pin.

5. A memory system comprising:

a plurality of DRAMs having receiver circuits adapted to interface with a plurality of signal drivers capable of providing both non-inverted and inverted address and command signal polarities to the plurality of DRAMs; and

a memory controller capable of enabling the plurality of DRAMs to accept either non-inverted or inverted signals using the programmable pin, which dynamically configures the polarities of address and command signals exchanged between a plurality of signal drivers and the plurality of DRAMs, such that simultaneous switching noise in the memory system is reduced.

6. The memory system of claim 5 wherein the pin is hardwired to the DRAMs.

7. A memory system comprising:

a module having a plurality of DRAMs with inputs and outputs and circuits to accept either non-inverted input signals or inverted input signals, wherein pre-selected DRAMs may operate in inverted mode with some critical signals remaining in a non-inverted mode;

a means connected to the circuit for changing modes to accept inverted input signals; and

a memory controller which is programmable to operate in non-inverted mode at power up and to change after it is programmed.

8. The memory system of claim 7 wherein the memory controller may operate in the inverted mode with some critical signals remaining in the non-inverted mode.

9. The memory system of claim 7 wherein a programmable pin is hard-wired to the module.

10. The memory system of claim 7 wherein the means for changing modes includes a pin that is controlled by the memory controller.