Semiconductor device with three-dimensional array structure

• US 7,646,664 B2
• Filed: 10/09/2007
• Issued: 01/12/2010
• Est. Priority Date: 10/09/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jung, Soon-Moon, Jang, Jae-Hoon, Jeong, Jae-Hun, Rah, Young-Seop, Park, Jun-Beom, Cho, Hoo-Sung
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US11/869,140
• Publication Number:
  US 20080084729A1
• Time in Patent Office: 826 Days
• Field of Search: 365/214
• US Class Current: 365/230.06
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/60 Peripheral circuit regions
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

Claims

1. A semiconductor memory device comprising:

a memory cell array including first and second memory cell blocks on respective first and second semiconductor layers, wherein the first memory cell block includes a first plurality of word lines on the first semiconductor layer including a first word line of the first plurality coupled to a first row of memory cells on the first semiconductor layer, wherein the second memory cell block includes a second plurality of word lines on the second semiconductor layer including a second word line of the second plurality coupled to a second row of memory cells on the second semiconductor layer, wherein the first plurality of word lines including the first word line is between the first and second semiconductor layers, and wherein the second semiconductor layer is between the first plurality of word lines and the second plurality of word lines;

a first row decoder adjacent the memory cell array wherein the first row decoder is configured to control the first word line;

a second row decoder adjacent the memory cell array wherein the second row decoder is configured to control the second word line;

a first wiring electrically connecting the first row decoder and the first word line, the first wiring including a first word line contact electrically contacting the first word line in a direction perpendicular with respect to the first semiconductor layer, a first metal line electrically connected to the first word line contact in a direction parallel with respect to the first semiconductor layer, and a first decoder contact electrically connected between the first metal line and the first decoder in a direction perpendicular with respect to the first semiconductor layer;

a second wiring electrically connecting the second row decoder and the second word line; and

an insulating layer on the second semiconductor layer and on the second word line wherein the second semiconductor layer is between the first semiconductor layer and the insulating layer,

wherein the first metal line is disposed on the insulating layer so that the insulating layer is between the first metal line and the first row decoder.

2. A semiconductor memory device according to claim 1 wherein the first and second row decoders are provided on a same side of the memory cell array.

3. A semiconductor memory device according to claim 1,

wherein the second wiring includes a second word line contact electrically contacting the second word line in a direction perpendicular with respect to the second semiconductor layer, a second metal line electrically connected to the second word line contact in a direction parallel with respect to the second semiconductor layer, and a second decoder contact electrically connected between the second metal line and the second decoder in a direction perpendicular with respect to the second semiconductor layer,

wheren the second metal line is disposed on the insulating layer so that the insulating layer is between the second metal line and the second row decoder.

4. A semiconductor memory device according to claim 3 further comprising:

a bit line on the insulating layer so that the insulating layer is between the bit line and the second semiconductor layer;

wherein at least one of the first and/or second metal lines is on a same side of the insulating layer as the bit line and wherein the at least one of the first and/or second metal lines and the bit line have a same thickness.

5. A semiconductor memory device according to claim 3 wherein the first and second word line contacts are provided on a same side of the memory cell array.

6. A semiconductor memory device according to claim 3 wherein the first and second word line contacts are provided on opposite sides of the memory cell array.

7. A semiconductor memory device according to claim 3 wherein the first metal line is between a portion of the second metal line and a portion of the second word line.

8. A semiconductor memory device according to claim 3 wherein the memory cell array further includes a third memory cell block on a third semiconductor layer with the second semiconductor layer between the first and third semiconductor layers, wherein the third memory cell block includes a third word line coupled to a third row of memory cells on the third semiconductor layer, and wherein the third word line is electrically coupled with the second word line and the second decoder through the second word line contact.

9. A semiconductor memory device according to claim 3 further comprising:

a bit line commonly coupled to the first memory cell block on the first semiconductor layer and the second memory cell block on the second semiconductor layer.

10. A semiconductor memory device according to claim 1 wherein the memory cell array further includes a third memory cell block on a third semiconductor layer spaced apart from the first and second semiconductor layers, wherein the third memory cell block includes a third word line coupled to a third row of memory cells on the third semiconductor layer, the semiconductor memory device further comprising:

a third row decoder configured to control the third word line, wherein the memory cell array is between the third row decoder and at least one of the first and/or second row decoders; and

a third wiring electrically connecting the third row decoder and the third word line.

11. A semiconductor memory device according to claim 1 further comprising:

a second memory cell array including third and fourth memory cell blocks on respective third and fourth semiconductor layers, wherein the third memory cell block includes a third word line coupled to a third row of memory cells on the third semiconductor layer, wherein the fourth memory cell block includes a fourth word line coupled to a fourth row of memory cells on the fourth semiconductor layer, wherein the third word line is between the third and fourth semiconductor layers, and wherein at least one of the first and/or second row decoders is between the first and second memory cell arrays.

12. A semiconductor memory device according to claim 11 further comprising:

a third row decoder adjacent the second memory cell array wherein the third row decoder is configured to control the third word line;

a fourth row decoder adjacent the second memory cell array wherein the second row decoder is configured to control the fourth word line, wherein at least one of the third and/or fourth row decoders is between the first and second memory cell arrays;

a third wiring electrically connecting the third row decoder and the third word line; and

a fourth wiring electrically connecting the fourth row decoder and the fourth word line.

13. A semiconductor memory device according to claim 12 wherein the first, second, third, and fourth row decoders are between the first and second memory cell arrays.

14. A semiconductor memory device according to claim 12 wherein the first and second row decoders are between the first and second memory cell arrays, and wherein the second memory cell array is between the first and second row decoders and the third and fourth row decoders.

15. A semiconductor memory device according to claim 1 wherein the memory cell array is between the first and second row decoders.

16. A semiconductor memory device according to claim 15 wherein the first memory cell block further includes a third word line coupled to a third row of memory cells on the first semiconductor layer, wherein the second memory cell block further includes a fourth word line coupled to a fourth row of memory cells on the second semiconductor layer, wherein the first row decoder comprises a first odd row decoder configured to control the first word line and a first even row decoder configured to control the third word line, and wherein the second row decoder comprises a second odd row decoder configured to control the second word line and a second even row decoder configured to control the fourth word line.

17. A semiconductor memory device according to claim 16 wherein the memory cell array is between the first odd and even row decoders and wherein the memory cell array is between the second odd and even row decoders.

18. A semiconductor memory device according to claim 17 wherein the first even row decoder and the second odd row decoder are on a same side of the memory cell array, and wherein the first odd row decoder and the second even row decoder are on a same side of the memory cell array.

19. A semiconductor memory device according to claim 1 wherein the first row decoder includes at least one transistor having portions thereof in the first semiconductor layer, and wherein the second row decoder includes at least one transistor having portions thereof in the first semiconductor layer.

20. A semiconductor memory device according to claim 1 wherein the first row decoder includes at least one first transistor, wherein the second row decoder includes at least one second transistor, wherein portions of the at least one first transistor and portions of the at least one second transistor are in different spaced apart semiconductor layers.

21. A semiconductor memory device according to claim 1 wherein each memory cell comprises a flash non-volatile memory cell transistor including a charge trapping layer between the respective word line and the respective semiconductor layer and a tunnel insulating layer between the charge trapping layer and the respective semiconductor layer.

22. A semiconductor memory device according to claim 1 wherein each memory cell of a respective row comprises one of a plurality of serially coupled memory cells in a different string of a NAND configuration.

23. A semiconductor memory device comprising:

a memory cell array including a memory cell block, wherein the memory cell block includes a first word line on a first semiconductor layer wherein the first word line is coupled to a first row of memory cells and a second word line coupled on a second semiconductor layer wherein the second word line is coupled to a second row of memory cells, and wherein the first word line is between the first and second semiconductor layers;

an odd row decoder adjacent the memory cell array wherein the odd row decoder is configured to control the first word line;

an even row decoder adjacent the memory cell array wherein the even row decoder is configured to control the second word line wherein the memory cell array is between the odd and even row decoders;

a first wiring electrically connecting the odd row decoder and the first word line; and

a second wiring electrically connecting the even row decoder and the second word line.

24. A semiconductor memory device comprising:

a memory cell array including first and second memory cell blocks on respective first and second semiconductor layers, wherein the first and second memory cell blocks include respective first and second pluralities of word lines, wherein the first plurality of word lines are coupled to respective first rows of memory cells on the first semiconductor layer, wherein the second pluralities of word lines are coupled to respective second rows of memory cells on the second semiconductor layer, and wherein the first word line is between the first and second semiconductor layers;

a row decoder adjacent the memory cell array wherein the row decoder is configured to control a first word line of the first plurality of word lines and a second word line of the second plurality of word lines; and

a wiring electrically connecting the first and second word lines and electrically connecting the first and second word lines with the row decoder.