Method and system for automatically calibrating intra-cycle timing relationships for sampling signals for an integrated circuit device

• US 7,646,835 B1
• Filed: 11/17/2003
• Issued: 01/12/2010
• Est. Priority Date: 11/17/2003
• Status: Active Grant

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Rozas, Guillermo J.
• Primary Examiner(s): Odom; Curtis B
• Application Number:
  US10/716,320
• Time in Patent Office: 2,248 Days
• Field of Search: 375371-376, 375/354, 714767-773, 365/194, 365/233
• US Class Current: 375/354
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1093 Input synchronization

Abstract

A method for automatically calibrating intra-cycle timing relationships between command signals, data signals, and sampling signals for an integrated circuit device. The method includes generating command signals for accessing an integrated circuit component, accessing data signals for conveying data for the integrated circuit component, and accessing sampling signals for controlling the sampling of the data signals. A phase relationship between the command signals, the data signals, and the sampling signals is automatically adjusted to calibrate operation of the integrated circuit device.

Claims

1. A method for automatically calibrating intra-cycle timing relationships between command signals, data signals, and sampling signals for an integrated circuit device, the method comprising:

generating command signals to access an integrated circuit component;

accessing data signals to convey data for the integrated circuit component;

accessing sampling signals to control sampling of the data signals; and

systematically altering a phase shift of the command signals, a phase shift of the data signals, and a phase shift of the sampling signals to determine a valid operation range of the integrated circuit device, wherein the valid operation range includes an optimal operation point for the integrated circuit device.

2. The method of claim 1, wherein the integrated circuit device comprises a DRAM component.

3. The method of claim 2, wherein said altering is performed by a memory controller coupled to the DRAM component.

4. The method of claim 2, wherein the DRAM component comprises a DDR DRAM component.

5. The method of claim 4, wherein the data signals comprise a plurality of data bus (DQ) signals for the DDR DRAM component.

6. The method of claim 5, wherein the sampling signals comprise a plurality of sampling bus (DQS) signals for the DDR DRAM component.

7. A system for automatically calibrating intra-cycle timing relationships between command signals, data signals, and sampling signals for an integrated circuit device, the system comprising:

a controller configured to generate command signals for accessing an integrated circuit component;

a delay calibrator integrated within the controller and configured to access data signals conveying data for the integrated circuit device and to access sampling signals for controlling sampling of the data signals, wherein the delay calibrator is further configured to systematically alter a phase shift of the command signals, a phase shift of the data signals, and a phase shift of the sampling signals to determine a valid operation range of the integrated circuit device; and

wherein the valid operation range includes an optimal operation point for the integrated circuit device.

8. The system of claim 7, wherein the integrated circuit device comprises a DRAM component.

9. The system of claim 8, wherein the DRAM component comprises a DDR DRAM component.

10. The system of claim 9, wherein the data signals comprise a plurality of DQ signals for the DDR DRAM component.

11. The system of claim 10, wherein the sampling signals comprise a plurality of DQS signals for the DDR DRAM component.

12. In a memory controller, a method for finding an operating mode for a DRAM component by altering intra-cycle timing relationships between command signals, data signals, and sampling signals for the DRAM component, the method comprising:

generating command signals to access a DRAM component;

accessing data signals to convey data for the DRAM component;

accessing sampling signals to control sampling of the data signals; and

systematically altering a phase shift of the command signals, a phase shift of the data signals, and a phase shift of the sampling signals to determine a valid operating range of the DRAM component.

13. The method of claim 12, further comprising:

performing a coarse calibration by altering the phase shift of the command signals, the phase shift of the data signals, and the phase shift of the sampling signals in accordance with a large step interval to determine if the valid operating range of the DRAM component exists; and

if the valid operating range exists, then performing a fine calibration by altering the phase shift of the command signals, the phase shift of the data signals, and the phase shift of the sampling signals in accordance with a small step interval to identify an optimal operating mode of the DRAM component.

14. The method of claim 13, wherein said performing a coarse calibration comprises simultaneously varying each of the phase shift of the command signal, the phase shift of the data signal, and the phase shift of the sampling signal by a five percent step increase.

15. The method of claim 13, wherein said performing a fine calibration comprises varying each of the phase shift of the command signal, the phase shift of the data signal, and the phase shift of the sampling signal one at a time by a two percent step increase.

16. The method of claim 13, further comprising configuring the memory controller to operate the DRAM component in the optimal operating mode.

17. The method of claim 12, wherein the DRAM component comprises a DDR DRAM component.

18. The method of claim 17, wherein the data signals comprise a plurality of DQ signals for the DDR DRAM component.

19. The method of claim 18, wherein the sampling signals comprise a plurality of DQS signals for the DDR DRAM component.

20. A computer readable media having stored thereon, computer-executable instructions that, if executed by a processor, cause the processor to perform a method for finding an operating mode for a DDR DRAM component by altering intra-cycle timing relationships between command signals, data signals, and sampling signals for the DDR DRAM component, the method comprising:

generating command signals to access a DDR DRAM component;

accessing DQ signals to convey DQ signals for the DDR DRAM component;

accessing DQS signals to control sampling of the DQ signals; and

systematically altering a phase shift of the command signals, a phase shift of the DQ signals, and a phase shift of the DQS signals to determine a valid operating range of the DDR DRAM component.

21. The computer readable media of claim 20, wherein the method further comprises:

performing a coarse calibration by altering the phase shift of the command signals, the phase shift of the data signals, and the phase shift of the sampling signals in accordance with a large step interval if the valid operating range of the DDR DRAM component exists; and

if the valid operating range exists, then performing a fine calibration by altering the phase shift of the command signals, the phase shift of the data signals, and the phase shift of the sampling signals in accordance with a small step interval to identify an optimal operating mode of the DDR DRAM component.

22. The computer readable media of claim 21, wherein the method further comprises configuring the memory controller to operate the DRAM component in the optimal operating mode.

23. In a memory controller, a method for finding an operating mode for a DDR DRAM component coupled to a PCB (printed circuit board) by altering intra-cycle timing relationships between command signals, data signals, and sampling signals for the DDR DRAM component, the method comprising:

generating command signals to access a DDR DRAM component;

accessing data signals to convey data for the DDR DRAM component;

accessing sampling signals to control sampling of the data signals; and

systematically altering a phase shift of the command signals, a phase shift of the data signals, and a phase shift of the sampling signals transmitted via a PCB to determine a valid operating range of the DDR DRAM component.