Unified digital architecture
First Claim
1. A unified serial link system for transmitting digital data across wired media including a transmitter and a receiver, comprising:
- the transmitter including a dual loop phase locked loop control circuit having a digital coarse loop for providing a full data rate phased lock loop (PLL) frequency control signal to an analog fine loop; and
the receiver including a phase locked loop control circuit and an over sampled half rate system, the receiver further comprising a signal edge comparator including a sample processing algorithm for centering a static edge of a signal in the middle between two signal samples, a bit edge correlation table for generating early and late signals based on the output of the comparator, and a multi-step phase rotator controlled by the generated signal.
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Abstract
A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.
18 Citations
16 Claims
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1. A unified serial link system for transmitting digital data across wired media including a transmitter and a receiver, comprising:
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the transmitter including a dual loop phase locked loop control circuit having a digital coarse loop for providing a full data rate phased lock loop (PLL) frequency control signal to an analog fine loop; and the receiver including a phase locked loop control circuit and an over sampled half rate system, the receiver further comprising a signal edge comparator including a sample processing algorithm for centering a static edge of a signal in the middle between two signal samples, a bit edge correlation table for generating early and late signals based on the output of the comparator, and a multi-step phase rotator controlled by the generated signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. The method of transmitting digital data across wired media between a transmitter and a receiver, comprising:
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providing a transmitter with a phase locked loop control circuit having a digital coarse loop and an analog fine loop; providing a full data rate PLL frequency control signal from the coarse loop to an analog fine loop; and providing a receiver including a phase locked loop control circuit and providing an over sampled half-rate system, the receiver further comprising a signal edge comparator, a bit edge correlation table including a sample processing algorithm for centering a static edge of a signal in the middle between two signal samples, a bit edge correlation table for generating early and late signals, a correlation table, and a multi-step phase rotator controlled by the generated signal. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification