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Unified digital architecture

  • US 7,646,839 B2
  • Filed: 10/13/2005
  • Issued: 01/12/2010
  • Est. Priority Date: 01/16/2001
  • Status: Expired due to Fees
First Claim
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1. A unified serial link system for transmitting digital data across wired media including a transmitter and a receiver, comprising:

  • the transmitter including a dual loop phase locked loop control circuit having a digital coarse loop for providing a full data rate phased lock loop (PLL) frequency control signal to an analog fine loop; and

    the receiver including a phase locked loop control circuit and an over sampled half rate system, the receiver further comprising a signal edge comparator including a sample processing algorithm for centering a static edge of a signal in the middle between two signal samples, a bit edge correlation table for generating early and late signals based on the output of the comparator, and a multi-step phase rotator controlled by the generated signal.

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