Instruction-associated processor resource optimization

• US 7,647,487 B2
• Filed: 09/28/2006
• Issued: 01/12/2010
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: Searete LLC (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Wood, JR., Lowell L., Myhrvold, Nathan P., Tegreene, Clarence T., Hillis, W. Daniel
• Primary Examiner(s): Chan, Eddie P
• Assistant Examiner(s): Faherty, Corey S
• Application Number:
  US11/540,910
• Publication Number:
  US 20070050556A1
• Time in Patent Office: 1,202 Days
• Field of Search: 712/23, 712/229
• US Class Current: 712/229
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

Embodiments include a device and a method. In an embodiment, a method applies a first resource management strategy to a first resource associated with a first processor and executes an instruction block in a first processor. The method also applies a second resource management strategy to a second resource of a similar type as the first resource and executes the instruction block in a second processor. The method further selects a resource management strategy likely to provide a substantially optimum execution of the instruction group from the first resource management strategy and the second resource management strategy.

Claims

1. A device comprising:

a processor having an associated hardware resource and a present context; and

a control unit associated with the processor and operable to fetch an instruction of an instruction group for execution by the processor;

receive a first and a second previously selected resource management policy associated in a computer-readable recordable medium with the instruction of the instruction group, the first previously selected resource management policy selected based on at least one of theoretical information or historical information as likely to provide a substantially optimum execution of the instruction group if the processor has a first predefined context, the second previously selected resource management policy selected based on at least one of theoretical information or historical information as likely to provide a substantially sub-optimum execution of the instruction group if the processor has a second predefined context, the first and the second previously selected resource management policy being received when the processor is scheduled to run the associated instruction of the instruction group;

determine whether a predetermined correlation exists between the present context of the processor and one of the first and the second predefined context to identify a corresponding previously selected resource management policy; and

apply the corresponding previously selected resource management policy.

7. The device of claim 1, wherein the hardware resource includes a memory cache.

8. The device of claim 1, wherein the hardware resource includes a branch predictor.

9. The device of claim 1, wherein the hardware resource includes at least one of a memory, a cache, a bus, a register-file, a port, and/or a functional unit.

10. The device of claim 1, wherein the control unit associated with the processor and operable to receive a first and a second previously selected resource management policy associated in a computer-readable recordable medium with the instruction group includes:

a control unit associated with the processor and operable to identify the corresponding previously selected resource management policy when a predetermined correlation exists between a present context of the first processor core and the first predefined context.

11. The device of claim 1, wherein the control unit associated with the processor and operable to receive a first and a second previously selected resource management policy associated in a computer-readable recordable medium with the instruction group includes:

a control unit associated with the processor and operable to identify the corresponding previously selected resource management policy when a predetermined correlation exists between a present context of the second processor core and the second predefined context.

12. The device of claim 1, wherein the control unit associated with the processor and operable to receive a first and a second previously selected resource management policy associated in a computer-readable recordable medium with the instruction group includes:

a control unit associated with the processor and operable to identify the first previously selected resource management policy as the corresponding previously selected resource management policy when a predetermined correlation exists between a present context of the first processor core and the first predefined context and when a predetermined correlation exists between a present context of the second processor core and the second predefined context.

13. The device of claim 1, wherein the control unit associated with the processor and operable to apply the previously selected resource management policy if a predetermined correlation exists between the present context of the processor and the predefined context includes:

a control unit associated with the processor and operable to apply the previously selected resource management policy when the processor is scheduled to run the associated instruction of the instruction group.

14. The device of claim 1, wherein the instruction group includes at least one of a functional instruction, a branching instruction, a memory instruction, and/or other instruction that may be executed by a processor.

15. The device of claim 1, wherein the instruction group includes at least one of a statement or a portion of a statement in a program.

16. The device of claim 1, wherein the instruction group includes at least two statements from a program.

17. The device of claim 1, wherein the instruction group includes at least one of a decoded instruction, a translated instruction, and/or a micro-operation.

18. The device of claim 1, wherein the control unit associated with the processor includes:

a control unit associated with the processor and operable to facilitate the processor executing the instruction.

2. A method comprising:

fetching an instruction of an instruction group to be executed by a processor core of a chip having at least two processor cores that each have access to a resource;

receiving a first and a second previously selected resource management policy that is logically associated in a computer-readable recordable medium with the instruction group, the first previously selected resource management policy having been selected based on at least one of theoretical information or historical information as likely to provide a substantially optimum execution of the instruction group if a first processor core has a first predefined context, the second previously selected resource management policy selected based on at least one of theoretical information or historical information as likely to provide a substantially sub-optimum execution of the instruction group if a second processor core has a second predefined context;

identify a corresponding previously selected resource management policy if a predetermined correlation exists between a present context of the first processor core and the first predefined context or if predetermined correlation exists between a present context of the second processor context and the second predefined context;

applying the identified corresponding previously selected resource management policy to the resource; and

executing the instruction by the processor core.

3. The method of claim 2, wherein the fetching an instruction of an instruction group to be executed by a processor core of a chip having at least two processor cores that each have access to a resource includes fetching an instruction of an instruction group to be executed by the first and second processor cores that each have access to a cache resource.

4. The method of claim 3, wherein the cache resource includes one of an on-chip cache or an off chip cache.

5. The method of claim 2, wherein the fetching an instruction of an instruction group to be executed by a processor core of a chip having at least two processor cores that each have access to a resource includes a fetching an instruction of an instruction group to be executed by the first and second processor cores that each have access to a branch predictor.

6. The method of claim 5, wherein the branch predictor includes static branch predictor or a dynamic branch predictor.

19. A method implemented in a computing device, the method comprising:

fetching but are not enough an instruction of an instruction group for execution by a processor having an associated hardware resource and a first execution context;

receiving a previously selected resource management policy associated in a computer-readable recordable medium with the instruction group, the previously selected resource management policy having been selected based on at least one of theoretical information or historical information as likely to provide a substantially optimum execution of the instruction group if the processor has a predefined context;

applying the previously selected resource management policy if a predetermined correlation exists between the present context of the processor and the predefined context;

applying a second hardware resource management policy to the instruction of the instruction group to produce a second execution context, the second hardware resource management policy selected based on at least one of theoretical information or historical information as likely to provide a substantially sub-optimum execution of the instruction group if the processor has a second predefined context;

comparing the first and second execution contexts; and

selecting one policy of the previously selected hardware resource management policy and the second hardware resource management policy in response to comparing the first and second execution contexts, wherein the selected one policy is stored for retrieval at a run time that is scheduled for the instruction of the instruction group.

20. The method of claim 19, wherein the fetching an instruction of an instruction group for execution by a processor having an associated hardware resource and a present context includes:

fetching an instruction of an instruction group for execution by a processor having a present context and an associated hardware resource managed by the processor.

21. The method of claim 19, further comprising:

facilitating execution of the instruction by the processor.

22. A computing device comprising:

means for fetching an instruction of an instruction group for execution by a processor having an associated hardware resource and a present context;

means for receiving a first and a second previously selected resource management policy associated in a computer-readable recordable medium with the instruction group, the first previously selected resource management policy having been selected based on at least one of theoretical information or historical information as likely to provide a substantially optimum execution of the instruction group if the processor has a first predefined context, the second previously selected resource management policy selected based on at least one of theoretical information or historical information as likely to provide a substantially sub-optimum execution of the instruction group if the processor has a second predefined context; and

means for applying one of the first and the second previously selected resource management policy if a predetermined correlation exists between the present context of the processor and one of the first and the second predefined context.

23. The computing device of claim 22, further comprising:

means for facilitating execution of the instruction by the processor.

24. A device comprising:

a processor having an associated hardware resource and a present context; and

a control unit associated with the processor and operable to fetch an instruction of an instruction group for execution by the processor;

receive a previously selected resource management policy associated in a storage device with the instruction group, the previously selected resource management policy selected based on at least one of theoretical information or historical information as likely to provide a substantially optimum execution of the instruction group if the processor has a predefined context in response to an application of a first test hardware resource management strategy to the hardware resource and to an application of a second test hardware resource management strategy to the hardware resource without a condition responsive to the application of the first test hardware resource management strategy, the second test hardware resource management policy selected based on at least one of theoretical information or historical information as likely to provide a substantially sub-optimum execution of the instruction group if the processor has a second predefined context, the previously selected resource management policy being associated with the instruction of the instruction group, and the previously selected resource management policy being received when the processor is scheduled to run the associated instruction of the instruction group; and

apply the previously selected resource management policy if a predetermined correlation exists between the present context of the processor and the first predefined context or apply the second test hardware resource management policy if a predetermined correlation exists between the present context of the processor and the second predefined context.

25. The device of claim 24, wherein the storage device includes a computer readable recordable medium.