Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias

• US 7,648,911 B2
• Filed: 05/27/2008
• Issued: 01/19/2010
• Est. Priority Date: 05/27/2008
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Do, Byung Tai, Pagaila, Reza A., Lin, Yaojian
• Primary Examiner(s): Lee; Calvin
• Application Number:
  US12/127,472
• Publication Number:
  US 20090294899A1
• Time in Patent Office: 602 Days
• Field of Search: 438/113, 438/629, 438/667, 438/675, 257/621, 257/698, 257E23141-179
• US Class Current: 438/667
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor die has a first insulating material disposed around a periphery of the die. A portion of the first insulating material is removed to form a through hole via (THV). Conductive material is deposited in the THV. A second insulating layer is formed over an active surface of the die. A first passive circuit element is formed over the second insulating layer. A first passive via is formed over the THV. The first passive via is electrically connected to the conductive material in the THV. The first passive circuit element is electrically connected to the first passive via. A third insulating layer is formed over the first passive circuit element. A second passive circuit element is formed over the third insulating layer. A fourth insulating layer is formed over the second passive circuit element. A plurality of semiconductor die is stacked and electrically interconnected by the conductive via.

Claims

1. A method of making a semiconductor device, comprising:

creating a gap between a plurality of semiconductor die;

depositing a first insulating material in the gap;

removing a portion of the first insulating material to form a through hole via (THV);

depositing conductive material in the THV;

forming a second insulating layer over an active surface of the semiconductor die;

forming a first passive circuit element over the second insulating layer; and

singulating the semiconductor wafer through the gap to separate the semiconductor die.

2. The method of claim 1, further including forming a conductive layer over the semiconductor die and first insulating material to electrically connect the conductive material in the THV to a contact pad on the semiconductor die.

3. The method of claim 1, further including:

forming a first passive via over the conductive material in the THV to electrically connect the first passive via to the conductive material in the THV; and

electrically connecting the first passive circuit element to the first passive via.

4. The method of claim 3, further including:

forming a third insulating layer over the first passive circuit element;

forming a second passive circuit element over the third insulating layer; and

forming a fourth insulating layer over the second passive circuit element.

5. The method of claim 4, further including:

forming a second passive via over the first passive via to electrically connect the second passive via to the first passive via; and

electrically connecting the second passive circuit element to the second passive via.

6. A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor die;

creating a gap between the semiconductor die;

depositing a first insulating material in the gap;

removing a portion of the first insulating material to form a through hole via (THV);

depositing a conductive material in the THV;

forming a second insulating layer over an active surface of the semiconductor die;

forming a first passive circuit element over the second insulating layer; and

singulating the semiconductor wafer through the gap to separate the semiconductor die.

7. The method of claim 6, further including forming a conductive layer over the semiconductor die and the first insulating material to electrically connect the conductive material in the THV to a contact pad on the semiconductor die.

8. The method of claim 6, further including:

forming a first passive via over the conductive material in the THV to electrically connect the first passive via to the conductive material in the THV; and

electrically connecting the first passive circuit element to the first passive via.

9. The method of claim 8, further including:

forming a third insulating layer over the first passive circuit element;

forming a second passive circuit element over the third insulating layer; and

forming a fourth insulating layer over the second passive circuit element.

10. The method of claim 9, further including:

forming a second passive via over the first passive via to electrically connect the second passive via to the first passive via; and

electrically connecting the second passive circuit element to the second passive via.

11. The method of claim 6, wherein the first semiconductor wafer is singulated through the THV to form a conductive half via.

12. The method of claim 6, wherein the first semiconductor wafer is singulated through the first insulating material to form a conductive full via.

13. A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor die;

creating a gap between the semiconductor die;

depositing a first insulating material in the gap;

removing a portion of the first insulating material to form a through hole via (THV);

depositing a conductive material in the THV;

forming a conductive layer over the semiconductor die and the first insulating material to electrically connect the conductive material in the THV to a contact pad on the semiconductor die;

forming a second insulating layer over an active surface of the semiconductor die;

forming a first passive circuit element over the second insulating layer;

forming a first passive via over the conductive material in the THV to electrically connect the first passive via to the conductive material in the THV;

electrically connecting the first passive circuit element to the first passive via; and

singulating the semiconductor wafer through the gap to separate the semiconductor die.

14. The method of claim 13, further including:

forming a third insulating layer over the first passive circuit element;

forming a second passive circuit element over the third insulating layer; and

forming a fourth insulating layer over the second passive circuit element.

15. The method of claim 14, further including:

forming a second passive via over the first passive via to electrically connect the second passive via to the first passive via; and

electrically connecting the second passive circuit element to the second passive via.

16. The method of claim 13, wherein the first semiconductor wafer is singulated through the THV to form a conductive half via.

17. The method of claim 13, wherein the first semiconductor wafer is singulated through the first insulating material to form a conductive full via.

18. The method of claim 13, further including:

stacking a plurality of semiconductor die; and

electrically interconnecting the plurality of semiconductor die through the conductive vias.

19. The method of claim 13, further including:

disposing a discrete device adjacent to semiconductor die; and

electrically connecting the discrete device to the conductive material in the THV.