P-channel MOS transistor, semiconductor integrated circuit device and fabrication process thereof

• US 7,649,232 B2
• Filed: 07/25/2005
• Issued: 01/19/2010
• Est. Priority Date: 03/29/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Microelectronics Limited (Fujitsu Limited)
• Inventors: Katakami, Akira, Tamura, Naoyoshi, Kawamura, Kazuo
• Primary Examiner(s): Wojciechowicz; Edward
• Application Number:
  US11/188,142
• Publication Number:
  US 20060220113A1
• Time in Patent Office: 1,639 Days
• Field of Search: 257/288, 257/335, 257/368, 257/383, 257/384, 257/401, 257/757
• US Class Current: 257/383
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A p-channel MOS transistor includes source and drain regions of p-type formed in a silicon substrate at respective lateral sides of a gate electrode wherein each of the source and drain regions of p-type includes any of a metal film region and a metal compound film region as a compressive stress source accumulating therein a compressive stress.

Claims

1. A p-channel MOS transistor, comprising:

a silicon substrate including a channel region therein;

a gate electrode formed on said silicon substrate in correspondence to said channel region via a gate insulation film;

a source extension region of p-type and a drain extension region of p-type formed in said silicon substrate at respective sides of said channel region;

a source region of p-type and a drain region of p-type formed in said silicon substrate at respective lateral sides of said gate electrode at respective outer sides of sidewall insulation films formed on respective sidewall surfaces of said gate electrode in a partially overlapping relationship with said source extension region of p-type and said drain extension region of p-type respectively;

a pair of trenches formed respectively in said source region of p-type and said drain region of p-type;

silicide films covering a bottom surface and a side surface of said pair of trenches, respectively;

a metal film or a conductive metal nitride film formed in each of said pair of trenches over a corresponding one of said silicide films, said metal film functioning as a compressive stress source,

wherein a bottom surface of said metal film or said conductive metal nitride film is located at a level lower than an interface between said channel region and said gate insulation film.

2. A p-channel MOS transistor as claimed in claim 1, wherein said compressive stress source is formed in said silicon substrate such that a bottom of said compressive stress source is separated from an interface between said silicon substrate and said gate insulation film by at least 10 nm.

3. The p-channel MOS transistor as claimed in claim 1, wherein said compressive stress source is formed in said silicon substrate such that a bottom of said compressive stress source is separated from an interface between said silicon substrate and said gate insulation film by at least 20 nm.

4. The p-channel MOS transistor as claimed in claim 1, wherein said compressive stress source comprises TiN or W.

5. The p-channel MOS transistor as claimed in claim 1, wherein said compressive stress source comprises a metal covered with a metal nitride film.

6. The p-channel MOS transistor as claimed in claim 1, wherein said silicide film has a lattice constant larger than a lattice constant of said silicon substrate.

7. The p-channel MOS transistor as claimed in claim 1, wherein said silicide film is selected from the group consisting of TiSi₂, NiSi, CoSi₂, TaSi₂, PtSi and IrSi.

8. The p-channel MOS transistor as claimed in claim 1, wherein each of said source region and drain region of p-type is formed with a depression, said depression including therein a contact layer of a p-type semiconductor layer grown epitaxially to said silicon substrate and containing Si as a primary component, said contact layer being doped with an impurity concentration level higher than an impurity concentration level of said source region or drain region of p-type, said compressive stress source being formed on said contact hole and filling said depression.

9. The p-channel MOS transistor as claimed in claim 8, wherein said contact layer comprises a Si epitaxial layer.

10. The p-channel MOS transistor as claimed in claim 8, wherein said contact layer comprises a SiGe epitaxial layer.

11. The p-channel MOS transistor as claimed in claim 1, further comprising an insulation film formed over said silicon substrate so as to cover said source region and drain region of p-type, and first and second contact plugs formed in said insulation film respectively in contact with said source region and drain region of p-type, said compressive stress source being formed at a tip end of said first contact plug in said source region of p-type and at a tip end of said second contact plug in said drain region of p-type.

13. The p-channel MOS transistor as claimed in claim 1, wherein said p-type source region and said p-type drain region have respective bottoms thereof located at a level lower than a bottom of said metal and/or metal compound film.

12. A semiconductor integrated circuit device comprising:

a silicon substrate defined with a first device region including a first channel region and a second device region including a second channel region by a device isolation region;

an n-channel MOS transistor formed on said first device region, comprising;

a first gate electrode of n-type formed on said silicon substrate via a first gate insulation film in correspondence to a first channel region;

a source extension region of n-type and a drain extension region of n-type formed in a part of said silicon substrate corresponding to said first device region at respective lateral sides of said first channel region; and

a source region and a drain region of n-type formed in a part of said silicon substrate corresponding to said first device region at respective lateral sides of said first gate electrode at outer sides of sidewall insulation films formed on respective sidewall surfaces of said first gate electrode so as to overlap partially with said source extension region of n-type and said drain extension region of n-type respectively;

a p-channel MOS transistor formed on said second device region, comprising;

a second gate electrode of p-type formed on said silicon substrate via a second gate insulation film in correspondence to a second channel region;

a source extension region of p-type and a drain extension region of p-type formed in a part of said silicon substrate corresponding to said second device region at respective lateral sides of said second channel region;

a source region and a drain region of p-type formed in a part of said silicon substrate corresponding to said second device region at respective lateral sides of said second gate electrode at outer sides of sidewall insulation films formed on respective sidewall surfaces of said second gate electrode so as to overlap partially with said source extension region of p-type and said drain extension region of p-type respectively;

a pair of trenches formed respectively in said source region of p-type and said drain region of p-type;

silicide films covering a bottom surface and a side surface of said pair of trenches, respectively;

silicide films covering a bottom surface and a side surface of said pair of trenches, respectively;

a metal film or a conductive metal nitride film formed in each of said pair of trenches over a corresponding one of said silicide films, said metal film functioning as a compressive stress source, a bottom surface of said metal film or said conductive metal nitride film being located at a level lower than an interface between said channel region and said gate insulation film,

an interlayer insulation film extending over said first and second device regions on said silicon substrate so as to cover said n-channel MOS transistor and said p-channel MOS transistor;

first and second contact plugs formed in said interlayer insulation film in correspondence to said source region and drain region of n-type;

third and fourth contact plugs formed in said interlayer insulation film in correspondence to said source region and drain region of p-type,

a first tip end part of said first contact plug causing a first tensile stress within said source region of n-type,

a second tip end part of said second plug causing a second tensile stress within said drain region of n-type,

a third tip end part of said third contact plug causing a third compressive stress within said source region of p-type,

a fourth tip end part of said fourth contact plug causing a fourth compressive stress within said drain region of p-type.