Field programmable gate array utilizing dedicated memory stacks in a vertical layer format
First Claim
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1. An electronic module comprising:
- a field-programmable gate array (FPGA);
an access lead network electrically coupled and proximate to the FPGA; and
a memory stack located external to the FPGA and electrically coupled to the access lead network, wherein the memory stack defines a planar surface and includes a plurality of layers, and wherein each of the layers comprises a memory IC;
wherein the memory stack further includes a conductive I/O pad located on the planar surface and configured to route an electrical signal between the memory IC and the access lead network; and
wherein the electronic module further includes a plurality of vertically-stacked prepackaged IC chips.
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Abstract
A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.
22 Citations
40 Claims
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1. An electronic module comprising:
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a field-programmable gate array (FPGA); an access lead network electrically coupled and proximate to the FPGA; and a memory stack located external to the FPGA and electrically coupled to the access lead network, wherein the memory stack defines a planar surface and includes a plurality of layers, and wherein each of the layers comprises a memory IC; wherein the memory stack further includes a conductive I/O pad located on the planar surface and configured to route an electrical signal between the memory IC and the access lead network; and wherein the electronic module further includes a plurality of vertically-stacked prepackaged IC chips. - View Dependent Claims (2, 3, 4, 5)
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6. An electronic module comprising:
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a field-programmable gate array (FPGA); an access lead network electrically coupled and proximate to the FPGA; and a memory stack located external to the FPGA and electrically coupled to the access lead network, wherein the memory stack defines a planar surface and includes a plurality of layers, and wherein each of the layers comprises a memory IC; wherein the memory stack further includes a conductive I/O pad located on the planar surface and configured to route an electrical signal between the memory IC and the access lead network; and wherein the electronic module further includes a plurality of vertically-stacked neo-chips. - View Dependent Claims (7, 8, 9, 10)
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11. An electronic module comprising:
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a field-programmable gate array (FPGA); an access lead network electrically coupled and proximate to the FPGA; and a memory stack electrically coupled to the access lead network, wherein the memory stack includes; a plurality of layers each comprising an integrated circuit; and a plurality of I/O terminals disposed on a planar surface of the stack, wherein the 110 terminals are configured to route electrical signals between the integrated circuits and the access lead network. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method comprising:
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disposing a field-programmable gate array (FPGA) proximate an access lead network; electrically connecting the FPGA to the access lead network; and electrically connecting a memory stack to the access lead network, wherein the memory stack includes a plurality of layers, each layer comprising an integrated circuit and a plurality of I/O terminals disposed on a surface of the stack, wherein the plurality of I/O terminals are configured to route electrical signals between the integrated circuits and the access lead network. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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Specification