Communication driver

• US 7,649,483 B1
• Filed: 12/20/2007
• Issued: 01/19/2010
• Est. Priority Date: 05/23/2000
• Status: Expired due to Term

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat, Roo, Pierte
• Primary Examiner(s): WILLIAMS, HOWARD L
• Application Number:
  US12/004,200
• Time in Patent Office: 761 Days
• Field of Search: 327/100, 327/103, 327/108, 327/126, 327/129, 327/131, 327132-136, 341/143, 341/144, 341/147, 375/295, 375/296
• US Class Current: 341/144
• CPC Class Codes: H03M 1/661 Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing
• CPC Class Codes: H03M 1/742 using current sources as quantisation value generators
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/03834 using pulse shaping

Abstract

A circuit includes T sets of digital to analog converters (DACs), each including N current sources and M delay elements. An output signal includes a sum of outputs of the N current sources. An input of a first one of the M delay elements and a control input of a first one of the N current sources receive a respective one of a plurality of decoded signals. T sets of first converters each have a feedback node, an output, and an input that communicates with the output signal of a respective one of the T sets of DACs. T second converters have inputs that communicate with respective ones of the feedback nodes of each of the T sets of first converters. A summer generates a difference signal that is based on the outputs of the T sets of first converters and outputs of the T second converters.

Claims

1. A circuit comprising:

T sets of digital to analog converters (DACs), each including;

N current sources, wherein an output signal comprises a sum of outputs of said N current sources; and

M delay elements, wherein an input of a first one of said M delay elements and a control input of a first one of said N current sources receive a respective one of a plurality of decoded signals, wherein an input of other ones of said M delay elements communicates with an output of preceding respective ones of said M delay elements, respectively, and wherein outputs of said other ones of said M delay elements control corresponding control inputs of said other ones of said N current sources;

T sets of first converters each having a feedback node, an output and an input that communicates with said output signal of a respective one of said T sets of DACs;

T second converters having inputs that communicate with respective ones of said feedback nodes of each of said T sets of first converters; and

a summer that generates a difference signal that is based on said outputs of said T sets of first converters and outputs of said T second converters.

2. The circuit of claim 1 further comprising a winding that includes a first terminal that communicates with first ones of said outputs of said T sets of first converters and a second terminal that communicates with second ones of said outputs of said T sets of first converters.

3. The circuit of claim 2 wherein said first ones and said second ones of said outputs of said T sets of first converters communicate with said summer.

4. The circuit of claim 1 wherein each of said T second converters comprises a single-ended to differential converter and wherein each of said T sets of first converters comprises a voltage to current converter.

5. The circuit of claim 1 further comprising T sets of filters arranged between said T sets of DACs and said T sets of first converters, respectively.

6. The circuit of claim 1 wherein each of said T sets of first converters comprise:

an amplifier including a first input that receives said output signal;

a transistor having an input that communicates with an output of said amplifier; and

a resistance that communicates with a first terminal of said transistor and a reference potential.

7. The circuit of claim 6 wherein said feedback node is arranged between said first terminal and said resistance and communicates with a second input of said amplifier.

8. The circuit of claim 1 further comprising T sets of delay circuits that are arranged between said outputs of said T sets of first converters, respectively, and said summer.

9. The circuit of claim 1 further comprising a decoder that generates said plurality of decoded signals.

10. The circuit of claim 1 further comprising:

a winding that includes a first terminal that communicates with first ones of said outputs of said T sets of first converters and a second terminal that communicates with second ones of said outputs of said T sets of first converters, and

wherein said outputs of said T second converters comprise partial differential replica signals, wherein a differential composite signal is sampled from said first and second terminals and wherein said difference signal comprises a differential received signal.

11. A method comprising:

providing T sets of digital to analog converters (DACs), each including;

N current sources, wherein an output signal comprises a sum of outputs of said N current sources; and

M delay elements, wherein an input of a first one of said M delay elements and a control input of a first one of said N current sources receive a respective one of a plurality of decoded signals, wherein an input of other ones of said M delay elements communicates with an output of preceding respective ones of said M delay elements, respectively, and wherein outputs of said other ones of said M delay elements control corresponding control inputs of said other ones of said N current sources;

providing T sets of first converters each having a feedback node, an output and an input that communicates with said output signal of a respective one of said T sets of DACs;

arranging inputs of T second converters in communication with respective ones of said feedback nodes of each of said T sets of first converters; and

generating a difference signal that is based on said outputs of said T sets of first converters and outputs of said T second converters.

12. The method of claim 11 further comprising arranging a first terminal of a winding in communication with first ones of said outputs of said T sets of first converters and a second terminal of said winding in communication with second ones of said outputs of said T sets of first converters.

13. The method of claim 12 wherein said first ones and said second ones of said outputs of said T sets of first converters communicate with a summer.

14. The method of claim 11 wherein each of said T second converters comprises a single-ended to differential converter and wherein each of said T sets of first converters comprises a voltage to current converter.

15. The method of claim 11 further comprising arranging T sets of filters between said T sets of DACs and said T sets of first converters, respectively.

16. The method of claim 11 wherein each of said T sets of first converters comprise:

an amplifier including a first input that receives said output signal;

a transistor having an input that communicates with an output of said amplifier; and

a resistance that communicates with a first terminal of said transistor and a reference potential.

17. The method of claim 16 further comprising arranging said feedback node between said first terminal and said resistance and in communication with a second input of said amplifier.

18. The method of claim 11 further comprising arranging T sets of delay circuits between said outputs of said T sets of first converters, respectively, and said summer.

19. The method of claim 11 further comprising providing a decoder that generates said plurality of decoded signals.

20. The method of claim 11 further comprising providing a winding that includes a first terminal that communicates with first ones of said outputs of said T sets of first converters and a second terminal that communicates with second ones of said outputs of said T sets of first converters, and wherein said outputs of said T second converters comprise partial differential replica signals, wherein a differential composite signal is sampled from said first and second terminals and wherein said difference signal comprises a differential received signal.