Network routing system for enhanced efficiency and monitoring capability

• US 7,649,885 B1
• Filed: 05/06/2002
• Issued: 01/19/2010
• Est. Priority Date: 05/06/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Foundry Networks Incorporated (Broadcom, Inc.)
• Inventors: Prince, Jeffrey A., Patel, Ronak, Davis, Ian Edward
• Primary Examiner(s): Patel; Jayanti K
• Assistant Examiner(s): SOL, ANTHONY M
• Application Number:
  US10/139,912
• Time in Patent Office: 2,815 Days
• Field of Search: None
• US Class Current: 370/392
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/16 Multipoint routing
• CPC Class Codes: H04L 45/306 Route determination based on the nature of the carried application
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 45/70 Routing based on monitoring results
• CPC Class Codes: H04L 47/22 Traffic shaping
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 47/39 Credit based
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags

Abstract

According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping. The integrated circuit may be associated with an IRAM, a CAM, a parameter memory configured to hold routing and/or switching parameters, which may be implemented as a PRAM, and an aging RAM, which stores aging information. The aging information may be used by a CPU coupled to the integrated circuit via a system interface circuit to remove entries from the CAM and/or the PRAM when an age count exceeds an age limit threshold for the entries.

Claims

1. A network device, comprising:

a plurality of ports each configured to receive data packets or to transmit data packets from the network device;

one or more memories;

a plurality of integrated port controllers, each integrated port controller circuit configured to receive data packets from one or more ports from the plurality of ports and to forward data packets to one or more ports from the plurality of ports;

a backplane; and

an adapter coupled to the plurality of integrated port controllers and to the backplane;

wherein each integrated port controller is configured to

receive a data packet received by the network device via a port from the plurality of ports,

determine forwarding information by performing one or more lookups in the one or more memories using information extracted from a header portion of the received packet, the forwarding information indicative of how the received data packet is to be forwarded in the network device, and

forward the data packet and the forwarding information to the adapter coupled to the integrated port controller;

wherein the adapter is configured to

receive a data packet and forwarding information for the data packet from an integrated port controller from the plurality of integrated port controllers, and

based upon the forwarding information, forward the data packet received by the adapter from the integrated port controller either to another integrated port controller coupled to the adapter or to the backplane.

2. A network device, as in claim 1, wherein each integrated port controller is configured to store the data packets received by the integrated port controller in a first memory from the one or more memories and to perform lookups using the first memory.

3. A network device, as in claim 2, wherein each integrated port controller includes a rate shaper configured to perform input rate shaping.

4. A network device as in claim 1, wherein each integrated port controller from the plurality of integrated port controllers is implemented in an ASIC.

5. A network device as in claim 1, wherein each integrated port controller from the plurality of integrated port controllers is implemented in a field programmable gate array.

6. A network device as in claim 1, selected from the group consisting of a router and a switch.

7. A network device as in claim 1, wherein the plurality of ports comprises one or more gigabit Ethernet ports.

8. A network device as in claim 1, wherein the plurality of ports comprises one or more 100/100 megabit Ethernet ports.

9. A network device as in claim 1, wherein the plurality of ports comprises one or more packets over SONET ports.

10. A network device as in claim 1, wherein the plurality of ports comprises one or more ATM ports.

11. A network device as in claim 1, wherein the one or more memories comprise a memory coupled to each integrated port controller providing buffers for the packet data portions of the data packets processed by the integrated port controller.

12. A network device as in claim 1, wherein the one or more memories comprise a content addressable memory (CAM) and a parameter memory coupled to each integrated port controller in the plurality of integrated port controllers, wherein the CAM coupled to an integrated port controller is used by the integrated port controller for performing lookups based upon information extracted from data packets processed by the integrated port controller, and results of the CAM lookup are used to perform lookups in the parameter memory.

13. A network device as in claim 1, further comprising a central processing unit coupled to the plurality of integrated port controllers.

14. A network device as in claim 1, wherein each integrated port controller comprises a reduced instruction set (RISC) processor.

15. The network device of claim 1 wherein the adapter is configured to receive a data packet from the backplane and forward the data packet received from the backplane to an integrated port controller coupled to the adapter.

16. A method performed by a network device for processing data packets, the method comprising:

receiving a plurality of data packets including a first data packet via a port of the network device;

forwarding the first data packet to a first integrated port controller from a plurality of integrated port controllers in the network device;

determining, at the first integrated port controller, forwarding information for the first data packet by performing one or more lookups in one or more memories coupled to the first integrated port controller using information extracted from a header portion of the first data packet, the forwarding information indicative of how the first data packet is to be forwarded in the network device;

forwarding the first data packet and the forwarding information from the first integrated port controller to an adapter in the network device, the adapter coupled to the plurality of integrated port controllers; and

based upon the forwarding information, forwarding the first data packet received by the adapter from the integrated port controller either to a second integrated port controller coupled to the adapter or to a backplane.

17. The method of claim 16, further comprising:

storing the data packet received by the first integrated port controller in a memory coupled to the first integrated port controller; and

performing a lookup using the memory coupled to the first integrated port controller.

18. The method of claim 16, wherein the plurality of data packets pertain to a particular class of service from a plurality of classes of service, the method further comprising regulating the incoming flow of the plurality of data packets in accordance with a quality of service associated with the particular class of service.

19. The method of claim 16, wherein determining the forwarding information comprises using the header portion to perform a lookup in a content addressable memory (CAM).

20. The method of claim 19, wherein determining the forwarding information comprises determining the forwarding information from a parameter random access memory (PRAM) using a result of the CAM lookup.

21. The method of claim 16 further comprising:

receiving, at the adapter, a second data packet from the backplane; and

forwarding the second data packet from the adapter to an integrated port controller coupled to the adapter.