Integrated optical transceiver circuit

• US 7,650,079 B2
• Filed: 01/07/2004
• Issued: 01/19/2010
• Est. Priority Date: 02/05/2003
• Status: Expired due to Fees

• Current Assignee: Alcatel SA (Nokia Corporation)
• Original Assignee: Alcatel SA (Nokia Corporation)
• Inventors: Preisach, Helmut
• Primary Examiner(s): Tran; Dzung D
• Application Number:
  US10/752,022
• Publication Number:
  US 20040151073A1
• Time in Patent Office: 2,204 Days
• Field of Search: 398/149, 398/155, 398/203, 398/207, 398/212
• US Class Current: 398/164
• CPC Class Codes: H04B 10/25 Arrangements specific to fibre transmission
• CPC Class Codes: H04B 10/40 Transceivers

Abstract

An integrated transceiver contains a optical equalizer for a distorted O/E-converted signal, an adaptive regenerator coupled to the equalizer, and a clock recovery circuit coupled to the adaptive regenerator. The transceiver has further an embedded processing unit and an integrated programmable memory which stores software program. The processing unit is coupled to adjust threshold values of the adaptive regenerator according to a software algorithm loaded into the memory.

Claims

1. An integrated transceiver comprising:

a first equalizer for a distorted O/E-converted optical signal;

an adaptive regenerator coupled to the equalizer;

a clock recovery circuit coupled to the adaptive regenerator;

an embedded processing unit; and

an integrated programmable memory for storing different pieces of software;

wherein said processing unit adjusts threshold values of said adaptive regenerator according to a software algorithm loaded into said memory.

2. The integrated transceiver according to claim 1, wherein said processing unit is further adapted to adjust said first equalizer under control of said software algorithm according to an error function determined by the adaptive regenerator.

3. The integrated transceiver according to claim 1, further comprising:

a second equalizer for electrical signals to be transmitted;

a second regenerator coupled to said second equalizer; and

a laser driver coupled to said second regenerator.

4. The integrated transceiver according to claim 1, wherein said adaptive regenerator comprises:

a decision circuit;

a quality monitor; and

a pseudo error counter,

wherein said processing unit adjusts phase and threshold values of said decision circuit according to said software algorithm using said quality monitor and pseudo error counter to determine optimized phase and threshold values.

5. The integrated transceiver according to claim 1, further comprising electrical line drivers for a regenerated electrical signal and a recovered clock signal.