Method for tuning chipset parameters to achieve optimal performance under varying workload types

• US 7,650,259 B2
• Filed: 10/01/2007
• Issued: 01/19/2010
• Est. Priority Date: 10/01/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Vanderpool, Brian T., Kirscht, Joseph A., Shedivy, David A., Blackmon, Herman L.
• Primary Examiner(s): Raymond; Edward
• Application Number:
  US11/865,545
• Publication Number:
  US 20090089554A1
• Time in Patent Office: 841 Days
• Field of Search: 702/182, 702/183, 702/185, 702/188, 702/75, 702/76, 702/78, 702/79, 702/176, 702/178, 711/100, 711/167, 712/26, 712/225
• US Class Current: 702/182
• CPC Class Codes: G06F 11/3428 Benchmarking
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G06F 2201/88 Monitoring involving counting

Abstract

A method, system, and computer program product for tuning a set of chipset parameters to achieve optimal chipset performance under varying workload characteristics. A set of workload characteristics of a current workload type is determined. An instruction stream is generated using weighted parameters derived from the set of workload characteristics of the current workload type. A set of chipset parameters is generated and integrated within the instruction stream. The instruction stream is loaded to one or more processors and executed to collect and analyze performance data relating to the chipset'"'"'s performance. The analysis includes comparing the set of performance data of a plurality of different instruction streams having the same set of workload characteristics. Each executed instruction stream is executed with at least one different combination of chipset parameters. A determination is made regarding which combination of chipset parameters provides the best performance data for the current workload.

Claims

1. A method for tuning a set of chipset parameters to achieve optimal chipset performance under varying workload characteristics comprising:

determining a set of workload characteristics of a current workload type;

generating an instruction stream using weighted parameters derived from the set of workload characteristics of the current workload type;

generating a set of modes and thresholds for a chipset being tested, wherein the combination of modes and thresholds define a combination of chipset parameters;

integrating the generated set of modes and thresholds within the instruction stream;

loading the instruction stream to one or more processors including a master processor and one or more slave processors;

executing the instruction stream for the one or more processors;

collecting a set of performance data from an executed instruction stream;

comparing the set of performance data of a plurality of different instruction streams having the same set of workload characteristics, wherein each executed instruction stream is executed with one or more different combinations of chipset parameters; and

determining the combination of chipset parameters that provides the best performance data for the current workload type.

2. The method of claim 1, further comprising:

quiescing processor threads of the one or more processors;

configuring and enabling a performance monitor for collecting the set of performance data;

determining a processor start time to mark the start of the re-execution of the previously quiesced processor threads;

re-executing the previously quiesced processor threads;

collecting the performance data from the re-executed processor threads;

completing re-execution of the processor threads of the at least one processor;

disabling the performance monitor to stop collecting the set of performance data; and

re-quiescing processor threads of the at least one processor; and

determining a processor end time to mark the completion of the re-executed processor threads.

3. The method of claim 1, further comprising:

detecting an actual workload type;

gathering a chipset performance data corresponding to the actual workload type; and

interpreting the chipset performance data to determine an optimal combination of chipset parameters for a Basic Input/Output System (BIOS) to set on a subsequent Initial Program Load (IPL).

4. The method of claim 3, further comprising:

detecting a change or a shift in an actual workload type; and

responsive to the change or the shift in the actual workload type, raising an interrupt to a System Management Interrupt (SMI) handler; and

modifying the chipset parameters to an optimal combination of chipset parameters.

5. A computer system comprising:

a processor unit;

a memory coupled to the processor unit; and

a ChipSet Parameter Optimization (CSPO) utility executing on the processor unit and having executable code for;

determining a set of workload characteristics of a current workload type;

generating an instruction stream using weighted parameters derived from the set of workload characteristics of the current workload type;

generating a set of modes and thresholds for a chipset being tested, wherein the combination of modes and thresholds define a combination of chipset parameters;

integrating the generated set of modes and thresholds within the instruction stream;

loading the instruction stream to one or more processors including a master processor and one or more slave processors;

executing the instruction stream for the one or more processors;

collecting a set of performance data from an executed instruction stream;

comparing the set of performance data of a plurality of different instruction streams having the same set of workload characteristics, wherein each executed instruction stream is executed with one or more different combinations of chipset parameters; and

determining the combination of chipset parameters that provides the best performance data for the current workload type.

6. The computer system of claim 5, the CSPO utility further having executable code for:

quiescing processor threads of the one or more processors;

configuring and enabling a performance monitor for collecting the set of performance data;

determining a processor start time to mark the start of the re-execution of the previously quiesced processor threads;

re-executing the previously quiesced processor threads;

collecting the performance data from the re-executed processor threads;

completing re-execution of the processor threads of the at least one processor;

disabling the performance monitor to stop collecting the set of performance data; and

re-quiescing processor threads of the at least one processor; and

determining a processor end time to mark the completion of the re-executed processor threads.

7. The computer system of claim 5, the CSPO utility further having executable code for:

detecting an actual workload type;

gathering a chipset performance data corresponding to the actual workload type; and

interpreting the chipset performance data to determine an optimal combination of chipset parameters for a Basic Input/Output System (BIOS) to set on a subsequent Initial Program Load (IPL).

8. The computer system of claim 7, the tree control utility further having executable code for:

detecting a change or a shift in an actual workload type; and

responsive to the change or the shift in the actual workload type, raising an interrupt to a System Management Interrupt (SMI) handler; and

modifying the chipset parameters to an optimal combination of chipset parameters.

9. A computer program product comprising:

a computer storage medium; and

program code on the computer storage medium that when executed provides the functions of;

determining a set of workload characteristics of a current workload type;

generating an instruction stream using weighted parameters derived from the set of workload characteristics of the current workload type;

generating a set of modes and thresholds for a chipset being tested, wherein the combination of modes and thresholds define a combination of chipset parameters;

integrating the generated set of modes and thresholds within the instruction stream;

loading the instruction stream to one or more processors including a master processor and one or more slave processors;

executing the instruction stream for the one or more processors;

collecting a set of performance data from an executed instruction stream;

comparing the set of performance data of a plurality of different instruction streams having the same set of workload characteristics, wherein each executed instruction stream is executed with one or more different combinations of chipset parameters; and

determining the combination of chipset parameters that provides the best performance data for the current workload type.

10. The computer program product of claim 9, the program code further provides the functions of:

quiescing processor threads of the one or more processors;

configuring and enabling a performance monitor for collecting the set of performance data;

determining a processor start time to mark the start of the re-execution of the previously quiesced processor threads;

re-executing the previously quiesced processor threads;

collecting the performance data from the re-executed processor threads;

completing re-execution of the processor threads of the at least one processor;

disabling the performance monitor to stop collecting the set of performance data; and

re-quiescing processor threads of the at least one processor; and

determining a processor end time to mark the completion of the re-executed processor threads.

11. The computer program product of claim 9, the program code further provides the functions of:

detecting an actual workload type;

gathering a chipset performance data corresponding to the actual workload type; and

interpreting the chipset performance data to determine an optimal combination of chipset parameters for a Basic Input/Output System (BIOS) to set on a subsequent Initial Program Load (IPL).

12. The computer program product of claim 11, the program code further provides the functions of:

detecting a change or a shift in an actual workload type; and

responsive to the change or the shift in the actual workload type, raising an interrupt to a System Management Interrupt (SMI) handler; and

modifying the chipset parameters to an optimal combination of chipset parameters.