Implementing a graphical program on a programmable hardware element to configure an instrument to perform a measurement function

• US 7,650,264 B2
• Filed: 05/22/2007
• Issued: 01/19/2010
• Est. Priority Date: 08/18/1997
• Status: Expired due to Fees

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Kodosky, Jeffrey L., Butler, Cary P., Odom, Brian K., Andrade, Hugo
• Primary Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US11/751,759
• Publication Number:
  US 20070225954A1
• Time in Patent Office: 973 Days
• Field of Search: 703/2, 703/22, 717/106, 717/125, 717/140, 702/57, 702/119, 702/119.57, 702/123, 702/127, 716/1, 716 16- 18, 345/700, 345/711
• US Class Current: 703/2
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test
• CPC Class Codes: G06F 2111/12 Symbolic schematics
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 8/34 Graphical or visual programming

Abstract

A computer-implemented system and method for generating a hardware implementation of graphical code. The method comprises first creating a graphical program. A first portion of the graphical program may optionally be compiled into machine code for execution by a CPU. A second portion of the graphical program is converted into a hardware implementation according to the present invention. The operation of converting the graphical program into a hardware implementation comprises exporting the second portion of the graphical program into a hardware description, wherein the hardware description describes a hardware implementation of the second portion of the graphical program, and then configuring a programmable hardware element utilizing the hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the second portion of the graphical program.

Claims

1. A computer-implemented method for configuring an instrument to perform a measurement function, wherein the instrument includes a programmable hardware element, the method comprising:

creating a block diagram, wherein the block diagram implements the measurement function;

wherein the block diagram comprises a plurality of nodes, wherein at least a subset of the plurality of nodes are connected to indicate data flow among the at least a subset of the plurality of nodes, wherein a first node of the plurality of nodes specifies control flow of data among one or more of the plurality of nodes;

generating a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation of the block diagram;

configuring the programmable hardware element in the instrument utilizing the hardware description, wherein after said configuring the programmable hardware element implements a hardware implementation of the block diagram;

wherein the programmable hardware element in the instrument is operable to perform the measurement function on a received signal.

2. The method of claim 1,

wherein the instrument comprises an image acquisition device, and wherein the image acquisition device comprises the programmable hardware element;

wherein the block diagram specifies an image processing function;

wherein the method further comprises;

acquiring an image of an object and storing the image; and

the programmable hardware element in the image acquisition device performing the image processing function on the image.

3. The method of claim 2, wherein the programmable hardware element performing the image processing function comprises:

the programmable hardware element in the image acquisition device determining characteristics of the image after performing the image processing function; and

the programmable hardware element in the image acquisition device performing an operation based on the determined characteristics of the image.

4. The method of claim 1, wherein the instrument comprises a smart camera, and wherein the smart camera comprises the programmable hardware element;

wherein the method further comprises;

the smart camera acquiring and storing an image of an object; and

the programmable hardware element in the smart camera performing an image processing function on the image.

5. The method of claim 4, wherein the programmable hardware element performing the image processing function comprises:

the programmable hardware element in the smart camera determining characteristics of the image after performing the image processing function; and

the programmable hardware element in the smart camera performing an operation based on the determined characteristics of the image.

6. The method of claim 1,

wherein the instrument comprises a smart sensor, and wherein the smart sensor comprises the programmable hardware element;

wherein the method further comprises;

the smart sensor acquiring a signal from the external source; and

the programmable hardware element in the smart sensor performing the measurement function on the signal.

7. The method of claim 6, wherein the smart sensor is one of a temperature sensor, pressure sensor, camera, microphone, flow sensor, position sensor, velocity sensor, acceleration sensor, vibration sensor, electromagnetic sensor, optical sensor, radiation sensor, or environment sensor.

8. The method of claim 1,

wherein the instrument comprises a fieldbus device, and wherein the fieldbus device comprises the programmable hardware element;

wherein the method further comprises;

the fieldbus device acquiring a signal from an external source; and

the programmable hardware element performing the measurement function on the signal.

9. The method of claim 1,

wherein the instrument comprises a programmable logic controller (PLC), and wherein the PLC comprises the programmable hardware element;

wherein the method further comprises;

the PLC acquiring a signal from an external source; and

the programmable hardware element in the PLC performing the measurement function on the signal.

10. The method of claim 1,

wherein the instrument comprises a computer-based instrument, wherein the computer-based instrument is configured as a card inserted into a slot of a computer system, and wherein the computer-based instrument comprises the programmable hardware element;

wherein the method further comprises;

the computer-based instrument acquiring a signal from an external source; and

the programmable hardware element in the computer-based instrument performing the measurement function on the signal.

11. The method of claim 1,

wherein the block diagram has an associated user interface portion;

the method further comprising;

presenting the user interface portion on a display during the programmable hardware element performing the measurement function on the received signal.

12. The method of claim 11,

wherein the user interface portion operates as a front panel for the instrument;

the method further comprising;

receiving user input to the user interface portion on the display to control the instrument during the programmable hardware element in the instrument performing the measurement function on the received signal.

13. The method of claim 11,

wherein the user interface portion includes one or more user interface objects;

wherein said generating includes incorporating a register in the hardware description for at least one of the user interface objects;

wherein the programmable hardware element in the instrument performing the measurement function on the received signal comprises accessing the register on the programmable hardware element to affect one of said user interface objects.

14. The method of claim 11, further comprising:

compiling the user interface portion into executable code for execution by a processor and storing the executable code in a memory;

the processor executing the executable code from the memory to present the user interface portion on the display during the programmable hardware element in the instrument executing to perform the measurement function on the signal.

15. The method of claim 14, wherein the instrument includes the processor and the memory.

16. The method of claim 14, wherein the instrument is coupled to a computer system, wherein the computer system includes the processor and the memory.

17. The method of claim 1, wherein the instrument further includes timer/counter logic, the method further comprising:

the timer/counter logic performing one of timing/counting operations during the programmable hardware element in the instrument performing the measurement function on the received signal.

18. The method of claim 1, further comprising:

the programmable hardware element performing the measurement function on the received signal; and

the programmable hardware element performing a process control function using the signal.

19. The method of claim 1, further comprising:

converting the hardware description into a net list; and

compiling the net list format into a hardware program file;

wherein said configuring the programmable hardware element includes downloading the hardware program file to the programmable hardware element to configure the programmable hardware element.

20. The method of claim 19, wherein said converting the hardware description into a net list includes:

utilizing at least one function block from a library of pre-compiled function blocks; and

utilizing hardware target specific information.

21. The method of claim 1, wherein said creating the block diagram includes:

arranging on the screen a plurality of nodes comprising the block diagram and interconnecting the plurality of nodes;

creating and storing data structures which represent the block diagram in response to said arranging and said interconnecting;

wherein said generating the hardware description comprises;

traversing the data structures;

converting the data structures into a hardware description format in response to said traversing.

22. The method of claim 1,

wherein said generating the hardware description comprises converting each of said nodes into a hardware description format.

23. The method of claim 1,

wherein, for the first node, said generating comprises:

determining inputs and outputs to/from the first node;

generating a hardware description of a control block which performs the control function indicated by the first node;

traversing input dependencies of the first node;

creating a hardware description of an AND gate, including listing connections of said input dependencies of the first node to said AND gate.

24. The method of claim 1, wherein a first portion of the block diagram is converted into a hardware description;

the method further comprising;

compiling a second portion of the block diagram into machine code for execution by the processor.

25. The method of claim 1, wherein the instrument includes a non-volatile memory coupled to the programmable hardware element, the method further comprising:

storing the hardware description into the non-volatile memory;

wherein said configuring the programmable hardware element comprises transferring the hardware description from the non-volatile memory to the programmable hardware element to produce the programmable hardware element.

26. The method of claim 1, further comprising:

the instrument acquiring a signal from an external source after said configuring;

the programmable hardware element in the instrument executing to perform the measurement function on the signal.

27. The method of claim 1,

wherein the block diagram is executable by a processor to perform the measurement function.

28. The method of claim 1,

wherein the first node indicates iteration for the one or more of the plurality of nodes in the block diagram.

29. The method of claim 1,

wherein the first node indicates looping for the one or more of the plurality of nodes in the block diagram.

30. The method of claim 1,

wherein the first node indicates conditional branching for the one or more of the plurality of nodes in the block diagram.

31. The method of claim 1,

wherein the first node indicates a first portion of the block diagram, wherein the first node indicates one of iteration, looping or conditional branching for the first portion of the block diagram.

32. The method of claim 1,

wherein the first node includes an interior portion, wherein a first portion of the block diagram is comprised in the interior portion, and wherein the first portion of the block diagram comprised in the interior portion of the first node execute according to control flow as indicated by the first node.

33. The method of claim 1, wherein said generating includes examining one or more first node parameters associated with the first node, and wherein said generating uses the one or more first node parameters in generating the hardware description.

34. The method of claim 33, wherein the first node is one of an iteration node or a looping node;

wherein the first node includes at least one of a period parameter and a phase delay parameter, wherein the period parameter indicates a period of execution for cycles of the first node, and wherein the phase delay parameter indicates a phase delay of cycles of the first node.

35. The method of claim 1, wherein the first node is an iteration node, wherein the iteration node indicates iteration of the one or more of the plurality of nodes in the block diagram for a plurality of times;

wherein the iteration node includes an iteration number which indicates a number of iterations for the block diagram; and

wherein said generating uses the iteration number in generating the hardware description.

36. The method of claim 1, wherein the first node is a looping node, wherein the looping node indicates looping of the one or more of the plurality of nodes in the block diagram for a plurality of times;

wherein the looping node includes a loop condition which indicates a number of executions for the block diagram; and

wherein said generating uses the loop condition in generating the hardware description.

37. A measurement system, comprising:

a computer system comprising a processor, memory and a display;

wherein the memory stores a block diagram, wherein the block diagram implements a measurement function, wherein the block diagram comprises a plurality of interconnected nodes which visually indicate functionality of the block diagram, wherein at least a subset of the plurality of nodes are connected to indicate data flow among the at least a subset of the plurality of nodes, wherein a first node of the plurality of nodes specifies control flow of data among one or more of the plurality of nodes;

wherein the memory also stores a software program which is executable to generate a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation of the block diagram; and

an instrument coupled to the computer system, wherein the instrument includes;

an input for acquiring a signal from an external source; and

a programmable hardware element coupled to the input, wherein the programmable hardware element in the instrument is configurable utilizing the hardware description, wherein after being configured the programmable hardware element implements a hardware implementation of the block diagram, and wherein the programmable hardware element in the instrument is operable to perform the measurement function on an acquired signal.

38. The measurement system of claim 37,

wherein the instrument comprises an image acquisition device, and wherein the image acquisition device comprises the programmable hardware element;

wherein the image acquisition device is operable to acquire an image of an object, and wherein the programmable hardware element in the image acquisition device is operable to perform an image processing function on the image.

39. The measurement system of claim 37,

wherein the instrument comprises a smart camera, and wherein the smart camera comprises the programmable hardware element;

wherein the smart camera is operable to acquire an image of an object and store the image; and

wherein the programmable hardware element in the smart camera is operable to perform an image processing function on the image.

40. The measurement system of claim 37,

wherein the instrument comprises a smart sensor, and wherein the smart sensor comprises the programmable hardware element;

wherein the smart sensor is operable to acquire a signal from an external source; and

wherein the programmable hardware element in the smart sensor is operable to perform the measurement function on the signal.

41. The measurement system of claim 37,

wherein the instrument comprises a fieldbus device, and wherein the fieldbus device comprises the programmable hardware element;

wherein the fieldbus device is operable to acquire the signal from the external source; and

wherein the programmable hardware element in the fieldbus device is operable to perform the measurement function on the signal.

42. The measurement system of claim 37,

wherein the instrument comprises a programmable logic controller (PLC), and wherein the PLC comprises the programmable hardware element;

wherein the PLC is operable to acquire the signal from the external source; and

wherein the programmable hardware element in the PLC is operable to perform the measurement function on the signal.

43. The measurement system of claim 37,

wherein the instrument comprises a computer-based instrument, wherein the computer-based instrument is configured as a card inserted into a slot of a computer system, and wherein the computer-based instrument comprises the programmable hardware element;

wherein the computer-based instrument is operable to acquire the signal from an external source; and

wherein the programmable hardware element in the computer-based instrument is operable to perform the measurement function on the signal.

44. The measurement system of claim 37,

wherein the block diagram has an associated user interface;

wherein the user interface portion is operable to be presented on a display during the programmable hardware element in the instrument executing to perform the measurement function on the signal.

45. The measurement system of claim 44,

wherein the user interface operates as a front panel for the instrument;

wherein the user interface is operable to receive user input to control the instrument while the programmable hardware element in the instrument executes to perform the measurement function on the signal.

46. The measurement system of claim 44,

wherein the user interface includes one or more user interface objects;

wherein, in generating a hardware description based on the block diagram, the software program is executable to incorporate a register in the hardware description for at least one of the user interface objects;

wherein the programmable hardware element in the instrument is operable to access a register on the programmable hardware element to affect one of said user interface objects.

47. The measurement system of claim 37, wherein the programmable hardware element in the instrument executes to perform a process control function using the signal.

48. The measurement system of claim 37, wherein the programmable hardware element comprises a field programmable gate array (FPGA).

49. The measurement system of claim 37, wherein the instrument includes a non-volatile memory coupled to the programmable hardware element;

wherein the non-volatile memory is operable to store the hardware description;

wherein the non-volatile memory is operable to transfer the hardware description to the programmable hardware element to produce the programmable hardware element.

50. The measurement system of claim 37,

wherein the block diagram is executable by the processor to perform the measurement function.

51. The measurement system of claim 37,

wherein the first node indicates iteration for the one or more of the plurality of nodes in the block diagram.

52. The measurement system of claim 37,

wherein the first node indicates looping for the one or more of the plurality of nodes in the block diagram.

53. The measurement system of claim 37,

wherein the first node indicates conditional branching for the one or more of the plurality of nodes in the block diagram.

54. The measurement system of claim 37,

wherein the first node indicates a first portion of the block diagram, wherein the first node indicates one of iteration, looping or conditional branching for the first portion of the block diagram.

55. The measurement system of claim 37,

wherein the first node includes an interior portion, wherein a first portion of the block diagram is comprised in the interior portion, and wherein the first portion of the block diagram comprised in the interior portion of the first node execute according to control flow as indicated by the first node.

56. The measurement system of claim 37, wherein said generating includes examining one or more first node parameters associated with the first node, and wherein said generating uses the one or more first node parameters in generating the hardware description.

57. The measurement system of claim 56, wherein the first node is one of an iteration node or a looping node;

wherein the first node includes at least one of a period parameter and a phase delay parameter, wherein the period parameter indicates a period of execution for cycles of the first node, and wherein the phase delay parameter indicates a phase delay of cycles of the first node.

58. The measurement system of claim 37, wherein the first node is an iteration node, wherein the iteration node indicates iteration of the one or more of the plurality of nodes in the block diagram for a plurality of times;

wherein the iteration node includes an iteration number which indicates a number of iterations for the block diagram; and

wherein said generating uses the iteration number in generating the hardware description.

59. The measurement system of claim 37, wherein the first node is a looping node, wherein the looping node indicates looping of the one or more of the plurality of nodes in the block diagram for a plurality of times;

wherein the looping node includes a loop condition which indicates a number of executions for the block diagram; and

wherein said generating uses the loop condition in generating the hardware description.