Microcomputer logic development system

• US 7,650,274 B2
• Filed: 02/15/2007
• Issued: 01/19/2010
• Est. Priority Date: 11/30/2001
• Status: Active Grant

• Current Assignee: Fujitsu Ten Limited (DENSO Corporation)
• Original Assignee: Fujitsu Ten Limited (DENSO Corporation)
• Inventors: Kashihara, Toshihiro, Imada, Shougo, Higuchi, Takashi
• Primary Examiner(s): Rodriguez; Paul L
• Assistant Examiner(s): Craig; Dwin M
• Application Number:
  US11/707,974
• Publication Number:
  US 20070143091A1
• Time in Patent Office: 1,069 Days
• Field of Search: 703/21, 703/24, 701/29
• US Class Current: 703/21
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A system for developing the preceding logic to be implemented in a built-in microcomputer that is used while being incorporated in an electronic control unit. The system includes: a motherboard having a first CPU, a first memory, and a first interface via which the motherboard communicates with the outside, interconnected over a first internal bus; a core board having a second CPU, a second memory, quasi microcomputer peripheral devices, which simulate by software the peripheral devices of a microcomputer, and a second interface via which the core board communicates with the outside, interconnected over a second internal bus; and a PCI bus that links the motherboard and the core board. The development system is substituted for the built-in microcomputer in order to implement the preceding logic.

Claims

1. A system for developing logic to be implemented in a built-in microcomputer that is used while being incorporated in an electric control unit, comprising:

a center block including at least a first central processing unit that processes the logic, a first memory in which data including a program in which the logic is implemented is stored, a first interface via which said center block communicates with the outside, and a first internal bus over which said first central processing unit, said first memory, and said first interface are interconnected;

a peripheral block including simulated microcomputer peripheral devices, a second interface via which said peripheral block communicates, and a second internal bus over which said simulated microcomputer peripheral devices and said second interface are interconnected; and

an internal bus over which said center block and peripheral block are interconnected, wherein;

said center block, said peripheral block, and said interface bus are substituted for said built-in microcomputer in order to implement the logic,

wherein said peripheral block further includes a second central processing unit, wherein

a control application composed of a temporal interrupt handling application that is run at regular intervals and a non-temporal interrupt handling application that is run irrespective of time with every occurrence of a predetermined event is stored in said first memory;

wherein

said first central processing unit has a virtual interrupt controller facility that performs at least temporal interrupt handling and non-temporal interrupt handling;

wherein

communication software that transmits or receives at least data and interrupt event information over said interface bus is installed in said first interface;

wherein

said second central processing unit communicates with said first interface using a second memory and a second interface to transfer an interrupt event and data over said interface bus, and

said simulated microcomputer peripheral devices include input facilities and output facilities,

wherein said input facilities include an input port, a latch port, an A/D converter, and a capture area, and said output facilities include an output port, a pulse transmitter, a comparator, and a serial interface, wherein

said control application is configured to issue a pulse transmission request using said comparator in response to an interrupt request issued from said peripheral block;

to transmit the pulse transmission request in at least one of immediate output mode in which a general output port facility included in an output terminal of said comparator is selected in order to immediately transmit the pulse transmission request, to select a timed output mode in which a comparative transmission facility is included in the output terminal of said comparator, and to determine a transmission time instant and a transmission level in order to set transmission, wherein

said simulated microcomputer peripheral devices included in said peripheral block are capable of handling any combination of pulse transmission requests transmitted from said control application in said immediate output mode or said timed output mode, and wherein

a delay time elapsing from the issuance of the pulse transmission request from said control application in said immediate output mode or said timed output mode to an actual transmission thereof to said peripheral block over said interface bus is corrected, and wherein the delay time is derived from said interface bus.

2. A system according to claim 1, wherein said second central processing unit has a throughput lower than that of said first central processing unit and which performs communication over said interface bus, and said peripheral block further includes a second memory in which data to be communicated is stored.

3. A system according to claim 1 or 2, further comprising an interface circuit block including input/output circuits, wherein:

said microcomputer logic development system is capable of being substituted for said electronic control unit with said interface circuit block connected to said peripheral block.

4. A system according to claim 3, wherein said center block, peripheral block and interface circuit block are formed with general-purpose circuit boards.

5. A system according to claim 2, wherein said second memory includes a common memory connected on said interface bus, and an internal memory connected to said second internal bus.

6. A system according to claim 1, wherein said center block includes a first timer.

7. A system according to claim 6, wherein said peripheral block includes a second timer used to manage time.

8. A system according to claim 1, further comprising a second simulated peripheral device added to said simulated peripheral devices included in said peripheral block.

9. A system according to claim 1, wherein:

said second memory includes a common memory connected on said interface bus; and

said simulated microcomputer peripheral devices transmit or receive data to or from said temporal interrupt handling application and said non-temporal interrupt handling application, which are stored in said first memory, by way of said common memory and said interface bus.

10. A system according to claim 9, wherein:

said common memory includes a communication synchronization counter; and

transmission and reception of data between said quasi microcomputer peripheral devices and said non-temporal interrupt handling application are synchronized based on said communication synchronization counter.

11. A system according to claim 1, wherein:

correction of the delay time is performed only on a type of signal for which the delay time is set to be corrected.

12. A system according to claim 1, wherein said microcomputer is used to control an internal combustion engine.

13. A system for developing logic to be implemented in a built-in microcomputer that is used while being incorporated in an electronic control unit, said system comprising:

a center block that includes a fast computing facility, a memory, and a communication facility;

a peripheral block that includes simulated microcomputer peripheral devices, a computing facility, and a communication facility, and that is connected to said center block over a PCI bus;

and an interface circuit block that includes circuits equivalent to hardware of an electronic control unit and that is connected to said peripheral block, wherein;

when said center block executes an application, at the start or end of a run unit of the application corresponding to a process that is nested within the application and that contains both arithmetic/logic operations and input/output operations relative to said memory, input/output information treated during input/output operations is gathered and communicated at one time to said peripheral block over said PCI bus, wherein

said center block includes a first block to execute the process that is nested with the application and that contains both arithmetic/logic operations and input/output operations, and a second block to execute a process that is nested within the application and that contains arithmetic/logic operations alone, and wherein

said center block is configured to give priority to the process nested within the application and executed by said first block over the process nested within the application and executed by said second block.

14. A system according to claim 13, wherein said center block transmits or receives information, which is treated during the input/output operations included in the process nested within the application and executed by said first block, synchronously with said peripheral block.

15. A system according to claim 13, wherein the process executed by said first block is divided into a time-synchronous interrupt handling portion that does not depend on an external state and contains input/output operations, and a non-time-synchronous interrupt handling portion that is executed synchronously with an event detected from an external state.

16. A system according to claim 15, wherein:

information about the event is contained in an interrupt flag information included in an interrupt signal to be transferred from said peripheral block to said center block; and

wherein when said first block activates the input/output operations and the arithmetic/logic operations in response to triggering of the interrupt signal, said first block handles each interrupt according to the interrupt flag information.

17. A system according to claim 15 or 16, further comprising an interrupt signal line over which an interrupt signal is sent from said peripheral block to said center block, and a sync signal line over which a sync signal is sent from said center block to said peripheral block between said center block and said peripheral block.

18. A system according to claim 17, wherein said peripheral block is configured to transmit the interrupt flag information over said interrupt signal line;

wherein a time-synchronous timing signal produced by said peripheral block is appended to the interrupt flag information; and

wherein if a plurality of flags are detected at a same sampling timing, said center block is configured to arbitrate handling of interrupts according to the priorities assigned to the interrupts and indicated by the flags.

19. A system according to claim 18 wherein, after said peripheral block is configured to transmit the interrupt flag information to said center block, said peripheral block clears the interrupt flag information unconditionally.

20. A system according to claim 19 wherein, when the interrupt flag information is not found, said peripheral block is configured to stop transmission to said center block.

21. A system according to claim 13, wherein said second block is configured to perform arithmetic/logic operations at regular intervals irrespective of the action of said peripheral block.

22. A system according to claim 13, wherein said center block is configured to allow said second block to execute the process nested within the application in an input/output completion wait state while said peripheral block is performing inputting/outputting.

23. A system according to claim 13, wherein said first block is configured to be activated with an interrupt signal sent from said peripheral block, and said second block is configured to be activated by an internal system of said center block.

24. A system according to claim 13, wherein:

when certain process included in the process nested within the application and executed by said second block of said center block is completed, said center block is configured to measure a processing time having elapsed since the previous termination of the processing nested within the application and assigned to said first block; and

if the processing time exceeds a predetermined time, transfer of data representing the result of the certain processing is inhibited.

25. A system according to claim 13, wherein:

said peripheral block includes a PCI memory in which input information to be sent to said center block and output information received from said center block are stored; and

wherein

said PCI memory is divided into a first storage area in which the input information is stored, and a second storage area in which the output information is stored.

26. A system according to claim 25 wherein, after the output information received from said center block is fully written in said PCI memory, said peripheral block is configured to read information from said PCI memory.

27. A system according to claim 25, wherein when said center block and said peripheral block communicate with each other over said PCI bus, only data values that have changed are sampled and transmitted.

28. A system according to claim 13, further comprising a plurality of peripheral blocks.

29. A system according to claim 28, wherein said plurality of peripheral blocks are configured to perform parallel processing of inputting/outputting relative to said center block.

30. A system according to claim 29, wherein said plurality of peripheral blocks are configured to perform parallel processing by transmitting or receiving a sync signal to or from one another.

31. A system according to claim 13, wherein when a run unit of the application corresponding to the process executed by said first block is large, said first block is configured to divide the run unit to perform the processing.

32. A system for developing logic to be implemented in a built-in microcomputer that is used while being incorporated in an electronic control unit, said system comprising:

a center block that includes a fast computing facility, a memory, and a communication facility,

a peripheral block that includes simulated microcomputer peripheral devices, a computing facility, and a communication facility, and that is connected to said center block over a PCI bus;

and an interface circuit block that includes circuits equivalent to hardware of an electronic control unit and that is connected to said peripheral block, wherein

when said center block executes an application, at the start or end of a run unit of the application corresponding to a process that is nested within the application and that contains both arithmetic/logic operations and input/output operations relative to said memory, input/output information treated during input/output operations is gathered and communicated at one time to said peripheral block over said PCI bus, wherein

said center block includes a first block to execute the process that is nested with the application and that contains both arithmetic/logic operations and input/output operations, and a second block to execute a process that is nested within the application and that contains arithmetic/logic operations alone, wherein

when a run unit of the application corresponding to the process executed by said first block is large, said first block is configured to divide the run unit to perform the processing, and

wherein the run unit of the application is divided into a run unit assigned a high priority and a run unit assigned a low priority.

33. A system for developing logic to be implemented in a built-in microcomputer that is used while being incorporated in an electronic control unit, said system comprising:

a center block that includes a fast computing facility, a memory, and a communication facility;

a peripheral block that includes simulated microcomputer peripheral devices, a computing facility, and a communication facility, and that is connected to said center block over a PCI bus;

and an interface circuit block that includes circuits equivalent to hardware of an electronic control unit and that is connected to said peripheral block, wherein

when said center block executes an application, at the start or end of a run unit of the application corresponding to a process that is nested within the application and that contains both arithmetic/logic operations and input/output operations relative to said memory, input/output information treated during input/output operations is gathered and communicated at one time to said peripheral block over said PCI bus, wherein

said center block includes a first block to execute the process that is nested with the application and that contains both arithmetic/logic operations and input/output operations, and a second block to execute a process that is nested within the application and that contains arithmetic/logic operations alone, wherein

when a run unit of the application corresponding to the process executed by said first block is large, said first block is configured to divide the run unit to perform the processing, and

wherein the run unit of the application is divided into two run units corresponding to a time-synchronous interrupt handling that does not depend on an external state and contains the input/output operations and a non-time-synchronous interrupt handling that is executed synchronously with an event whose information is detected from the external state.

34. A system according to claim 33, wherein each of the time-synchronous interrupt handling and non-time-synchronous interrupt handling is subdivided into a first run unit assigned a high priority and a second run unit assigned a low priority.