Flash memory driver

• US 7,650,458 B2
• Filed: 06/23/2006
• Issued: 01/19/2010
• Est. Priority Date: 06/23/2006
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Patel, Sachin C., Rogers, Andrew, Gopalan, Yadhu N.
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US11/474,234
• Publication Number:
  US 20070300009A1
• Time in Patent Office: 1,306 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Various flash management techniques may be described. An apparatus may comprise a processor, a flash memory coupled to the processor, and a flash management module. The flash management module may be executed by the processor to receive a write transaction request to write data to a flash memory, and write the data to a set of multiple discontiguous logical sectors corresponding to a set of physical sectors of the flash memory in a single atomic operation. Other embodiments are described and claimed.

Claims

1. An article comprising a computer-readable storage medium containing instructions that if executed enable a system to receive a write transaction request to write data to a flash memory, assign a sequence number to said write transaction request, and write said data and said sequence number to a set of multiple discontiguous logical sectors corresponding to a set of physical sectors in a spare area of said flash memory in a single atomic operation without allowing for partial writing of said data.

2. The article of claim 1, further comprising instructions that if executed enable the system to receive a request to append data to a file, update a directory entry with a new file size in random access memory, update a file allocation table in said random access memory, and send said write transaction request with said directory entry update information, said file allocation table update information, and said data.

3. The article of claim 1, further comprising instructions that if executed enable the system to maintain a mapping between said logical sectors and said physical sectors in a mapping table.

4. The article of claim 1, further comprising instructions that if executed enable the system to erase data from a set of previous physical sectors corresponding to said logical sectors once said data for said write transaction has been completely written.

5. The article of claim 1, further comprising instructions that if executed enable the system to write a control sector with metadata for said write transaction request.

6. The article of claim 1, further comprising instructions that if executed enable the system to write a control sector with sector information for said write transaction request, said sector information including at least one of transaction information, logical sector mapping information, or a transaction sequence number.

7. The article of claim 1, further comprising instructions that if executed enable the system to update a last known good sector number once said write transaction has been committed, wherein logical sectors, if any, with a same logical sector address and an older sequence number are interpreted as dirty.

8. The article of claim 1, said machine-readable storage medium comprising a computer-readable medium.

9. A method, comprising:

receiving a write transaction request to write data to a flash memory;

assigning a sequence number to said write transaction request; and

writing said data and said sequence number to a set of multiple discontiguous logical sectors corresponding to a set of physical sectors of said flash memory in a single atomic operation, wherein said atomic operation either completely writes said data or writes no data and does not allow for partial writing of said data.

10. The method of claim 9, comprising

receiving a request to append data to a file;

updating a directory entry with a new file size in random access memory;

updating a file allocation table in said random access memory; and

sending said write transaction request with said directory entry update information, said file allocation table update information, and said data.

11. The method of claim 9, comprising maintaining a mapping between said logical sectors and said physical sectors in a mapping table.

12. The method of claim 9, comprising:

writing said data and sequence number to said logical sectors in a spare area of said flash memory; and

erasing data from a set of previous physical sectors corresponding to said logical sectors once said data for said write transaction has been completely written.

13. The method of claim 9, comprising writing a control sector with metadata for said write transaction request.

14. The method of claim 9, comprising writing a control sector with sector information for said write transaction request, said sector information including at least one of transaction information, logical sector mapping information, or a transaction sequence number.

15. The method of claim 9, comprising:

writing said data and said sequence number in a spare area for said flash memory;

committing said write transaction; and

updating a LKG sector number once said write transaction has been committed.

16. An apparatus, comprising:

a processor;

a flash memory coupled to said processor; and

a flash management module that when executed by said processor is arranged to receive a write transaction request to write data to a flash memory, assign a sequence number to said write transaction request, and write said data and said sequence number to a set of multiple discontiguous logical sectors corresponding to a set of physical sectors of said flash memory in a single atomic operation without allowing for partial writing of said data.

17. The apparatus of claim 16, comprising:

a computer-readable media comprising a file system;

the flash management module comprising a flash abstraction layer communicatively coupled to said file system and a flash media driver communicatively coupled to said flash abstraction layer; and

said flash memory communicatively coupled to said flash media driver.

18. The apparatus of claim 17, said file system to receive an append request to append data to a file, and invoke said write transaction request in response to said append request.

19. The apparatus of claim 17, said flash abstraction layer to write said data to said logical sectors in a spare area of said flash memory, and erase data from a set of previous physical sectors corresponding to said logical sectors once said data for said write transaction has been completely written.

20. The apparatus of claim 17, said flash abstraction layer write said data and said sequence number in a spare area for said flash memory, commit said write transaction, and update a LKG sector number once said write transaction has been committed.