Fabricating method for thin film transistor array substrate and thin film transistor array substrate using the same

• US 7,651,899 B2
• Filed: 12/11/2006
• Issued: 01/26/2010
• Est. Priority Date: 12/29/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lim, Byoung Ho
• Primary Examiner(s): Hu; Shouxiang
• Application Number:
  US11/636,605
• Publication Number:
  US 20070166894A1
• Time in Patent Office: 1,142 Days
• Field of Search: 438/30, 438/151, 438/155, 438/158, 257/59, 257/72, 257/E21.414, 349/141
• US Class Current: 438/158
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

A method of fabricating a thin film transistor array substrate and a thin film transistor array substrate using the same is disclosed. Picture quality deterioration may be prevented.

Claims

1. A method of fabricating a thin film transistor array substrate, comprising:

sequentially disposing a transparent conductive material and a metal material on a substrate;

with a first mask process using a first mask, patterning the transparent conductive material and the metal material to provide a gate metal pattern including a gate line, a gate electrode of a thin film transistor connected to the gate line, a gate pad extending from the gate line, a common line substantially parallel to the gate line and a common electrode substantially vertical-extended from the common line and formed in a substantially finger structure, and forming a pixel electrode providing a horizontal electric field along with the common electrode, wherein the gate line, the gate electrode, the gate pad, the common line and the common electrode have a double layer structure including the transparent conductive material and the metal material and wherein the pixel electrode is a single layer structure made from the transparent conductive material, wherein the first mask is a half-transmitting mask in which a shielding portion is formed at an area corresponding to the gate metal pattern and a half-transmitting portion is formed at an area corresponding to the pixel electrode;

sequentially disposing a first insulating material, a first semiconductor material and a second semiconductor material on the substrate provided with the gate metal pattern and the pixel electrode;

with a second mask process using a second mask, patterning the first insulating material, the first semiconductor material and the second semiconductor material to provide a gate insulating film having a first contact hole exposing the pixel electrode, an active layer made from the first semiconductor material on the gate insulating film overlapping with the gate electrode, and an ohmic contact layer made from the second semiconductor material on the active layer, wherein the active layer is formed above the gate electrode to have a same area as an area where the gate electrode is formed or a substantially narrower area than the area where the gate electrode is formed;

disposing a source/drain metal material on the substrate provided with the first contact hole, the active layer and the ohmic contact layer;

with a third mask process using a third mask, patterning the source/drain metal material to provide a data metal pattern including a data line crossing the gate line and having the gate insulating film therebetween, a drain electrode contacted, via the first contact hole, with the pixel electrode, a source electrode separated from the drain electrode with a channel of a thin film transistor therebetween and a data pad extending from the data line;

entirely coating a second insulating material on the substrate provided with the data metal pattern; and

with a fourth mask process using a fourth mask, patterning the second insulating material to provide a second contact hole for exposing the gate pad and a third contact hole for exposing the data pad.

2. The method of fabricating the thin film transistor array substrate as claimed in claim 1, wherein the second mask is a half-transmitting mask in which a shielding portion is formed at an area corresponding to the active layer and the ohmic contact layer, and a half-transmitting portion is formed at an area corresponding to an area of gate insulating film other than an area provided with the active layer, the ohmic contact layer and the first contact hole.

4. The method of fabricating the thin film transistor array substrate as claimed in claim 1, wherein the fourth mask process further includes the step of removing the second insulating material provided at the third contact hole.

3. The method of fabricating the thin film transistor array substrate as claimed in claim I, wherein the third mask process further includes the step of removing an ohmic contact layer provided on the channel portion of the thin film transistor.

5. A method of fabricating a thin film transistor array substrate, comprising:

with a first mask process using a first mask, patterning a transparent conductive material and a metal material to provide a gate metal pattern including a gate line, a common line substantially parallel to the gate line and a common electrode substantially vertically-extended from the common line, and forming a pixel electrode on a substrate, wherein the gate line and the common line have a double layer structure including the transparent conductive material and the metal material and wherein the first mask is a half-transmitting mask so that the gate line and the common line have a double layer structure including the transparent conductive material and the metal material, and the pixel electrode has a single layer made from the transparent conductive material, wherein the first mask includes a shielding portion disposed at an area corresponding to the gate patterns and wherein a half-transmitting portion is positioned at an area corresponding to the common electrode and the pixel electrode, and a transmitting portion is positioned at a different area;

sequentially disposing a first insulating material, a first semiconductor material and a second semiconductor material on the substrate provided with the gate metal pattern and the pixel electrode;

with a second mask process using a second mask, patterning the first insulating material, the first semiconductor material and the second semiconductor material, and forming an active layer made from the patterned first semiconductor material, and an ohmic contact layer made from the patterned second semiconductor material on the active layer, wherein the second mask is a half transmitting mask and wherein the active layer is formed above the gate electrode to have a same area as an area where the gate electrode is formed or a substantially narrower area than an area where the gate electrode is formed;

disposing a source/drain metal material on the substrate, the active layer and the ohmic contact layer;

with a third mask process using a third mask, patterning the source/drain metal material to provide a data metal pattern;

entirely coating a second insulating material on the substrate provided with the data metal pattern; and

with a fourth mask process using a fourth mask, patterning the second insulating material.

6. The method of fabricating the thin film transistor array substrate as claimed in claim 5, wherein the second mask includes a shielding portion disposed at an area corresponding to the active layer and the ohmic contact layer and wherein a half-transmitting portion is positioned at an area corresponding to a first contact hole for exposing the pixel electrode, and a transmitting portion is positioned at a different area.