Electronic device including trenches and discontinuous storage elements and processes of forming and using the same

• US 7,651,916 B2
• Filed: 01/24/2007
• Issued: 01/26/2010
• Est. Priority Date: 01/24/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Hong, Cheong Min, Li, Chi-Nan
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US11/626,768
• Publication Number:
  US 20080173923A1
• Time in Patent Office: 1,098 Days
• Field of Search: 438/259, 438/260, 438/288, 438/962, 257/E21.692, 257/E21.693
• US Class Current: 438/259
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. Processes of forming and using the electronic device are also described.

Claims

1. A process of forming an electronic device comprising:

forming a first trench within a substrate, wherein the first trench extends from a primary surface of the substrate and has a first wall and a first bottom;

forming discontinuous storage elements over the primary surface and within the first trench;

forming a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench;

forming a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench; and

removing a portion of the discontinuous storage elements to form a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench.

2. The process of claim 1, wherein:

forming the first gate electrode comprises;

substantially conformally depositing a first gate electrode material over the primary surface of the substrate and within the first trench; and

anisotropically etching the gate electrode material to remove a portion of the first gate electrode material from over the primary surface of the substrate to form the first gate electrode; and

forming the second gate electrode comprises;

substantially conformally depositing a second gate electrode material over the primary surface of the substrate and the first gate electrode and within the first trench; and

anisotropically etching the second gate electrode material to remove a portion of the second gate electrode material from over the primary surface of the substrate to for the second gate electrode.

3. The process of claim 1, wherein:

forming the discontinuous storage elements is part of forming a charge storage stack; and

forming the first gate electrode comprises exposing a portion of the charge storage stack.

4. The process of claim 3, wherein removing the portion of the discontinuous charge storage elements comprises etching the portion of the charge storage stack.

5. The process of claim 3, wherein removing the portion of the discontinuous charge storage elements comprises thermally consuming the pod ion of the discontinuous charge storage elements.

6. The process of claim 1, wherein:

forming the discontinuous storage element is performed after forming the first gate electrode; and

removing the portion of the discontinuous charge storage elements is performed after forming the second gate electrode.

7. The process of claim 6, further comprising removing another portion of the discontinuous charge storage elements before forming the second gate electrode, wherein the another portion of the discontinuous storage elements overlies the first gate electrode before removing the another portion.

8. The process of claim 1, further comprising forming a first doped portion of the substrate, wherein the first doped portion lies adjacent to the first trench and spaced apart from the first bottom.

9. The process of claim 8, further comprising forming a second doped portion of the substrate, wherein the second doped portion lies along the first bottom of the first trench.

10. The process of claim 9, wherein the first and second doped portions of the substrate are source/drain regions.

11. The process of claim 10, wherein the electronic device comprises a memory cell that includes the first set of discontinuous storage elements, the first gate electrode, the second gate electrode, and the first and second doped portions of the substrate.

12. The process of claim 10, further comprising forming a second trench within the substrate, wherein:

the second trench is spaced apart from the first trench and extends from the primary surface of the substrate and has a second wall and a second bottom; and

forming the first doped portion of the substrate is performed such that the first doped region extends to the first wall of the first trench and to the second wall of the second trench.

13. The process of claim 12, further comprising forming a third doped region of the substrate, wherein:

the third doped portion lies along the second bottom of the second trench;

the third doped portion is spaced apart from the second wall; and

the first doped portion is spaced apart from the first wall.

14. The process of claim 13, further comprising:

forming a third gate electrode within the second trench and adjacent to the second wall and overlying the second bottom of the second trench; and

forming a fourth gate electrode within the second trench and adjacent to the third gate electrode and overlying the second bottom of the second trench,

wherein removing the portion of the discontinuous storage elements also forms a second set of discontinuous storage elements, wherein the second set of the discontinuous storage elements overlies the second bottom of the second trench.

15. The process of claim 1, wherein removing the portion of the discontinuous storage elements is performed after forming The first gate electrode and before forming the second gate electrode.

16. The process of claim 15, wherein:

forming the first gate electrode comprises forming a control gate electrode; and

forming the second gate electrode comprises forming a select gate electrode.

17. The process of claim 16, further comprising forming an insulating layer along the bottom of the first trench after removing The portion of the discontinuous storage elements and before forming the second gate electrode.

18. The process of claim 16, wherein removing the portion of the discontinuous storage elements is performed such that the first set of discontinuous storage elements lie between the first wall and the control gate electrode.

19. The process of claim 16, wherein removing the portion of the discontinuous storage elements and forming the second gate electrode are performed such that substantially no discontinuous storage element lies between the control gate electrode and the select gate electrode.

20. The process of claim 15, wherein the electronic device comprises a memory cell that includes the first set of discontinuous storage elements, the first gate electrode, and the second gate electrode.