Buffer circuit, amplifier circuit, and test apparatus
First Claim
Patent Images
1. A buffer circuit that outputs a signal according to an input signal, comprising:
- a first receiving transistor that receives the input signal through its base terminal;
a first clamp transistor having polarity the same as that of the first receiving transistor, of which an emitter terminal and a collector terminal are connected to corresponding terminals of the first receiving transistor and which receives a first clamp voltage restricting a signal level output from the buffer circuit through its base terminal; and
a first current defining section that is commonly provided for the first receiving transistor and the first clamp transistor and defines a total amount of emitter currents flowing into the first receiving transistor and the first clamp transistor, whereinthe buffer circuit outputs an output signal according to an emitter voltage of the first receiving transistor, the buffer circuit further comprising;
a first output transistor having polarity different from that of the first receiving transistor and the first clamp transistor, of which a base terminal is connected to the emitter terminal of the first transistor and the emitter terminal of the first clamp transistor and which outputs the output signal according to a receiving signal through its base terminal, whereinthe first receiving transistor outputs, when a signal level of the input signal is within a range defined by the first clamp voltage, a signal having a signal level according to the input signal,the first clamp transistor outputs, when the signal level of the input signal is out of a range defined by the first clamp voltage, a signal having a signal level according to the first clamp voltage,the first receiving transistor generates a signal having a signal level obtained by adding or subtracting a voltage between the base and the emitter to or from the signal level of the input signal through its emitter terminal,the first clamp transistor generates a signal having a signal level obtained by adding or subtracting a voltage between the base and the emitter to or from the first clamp voltage through its emitter terminal, andthe first output transistor outputs an output signal having a signal level obtained by subtracting or adding a voltage between the base and the emitter from or to a signal level of the signal received through its base terminal, the buffer circuit further comprising;
a second receiving transistor having polarity different from that of the first receiving transistor, which is provided in parallel with the first receiving transistor and receives the input signal through its base terminal;
a second clamp transistor having polarity the same as that of the second receiving transistor, of which an emitter terminal and a collector terminal are connected to corresponding terminals of the second receiving transistor and which receives a second clamp voltage smaller than the first clamp voltage through its base terminal;
a second current defining section that is commonly provided for the second receiving transistor and the second clamp transistor and defines a total amount of emitter currents flowing into the second receiving transistor and the second clamp transistor;
a second output transistor having polarity different from that of the second receiving transistor and the second clamp transistor, of which a base terminal is connected to an emitter terminal of the second transistor and an emitter terminal of the second clamp transistor and which outputs the output signal according to a receiving signal through its base terminal;
a first operation bias resistor that is provided between the emitter terminal of the first output transistor and the base terminal of the second clamp transistor; and
a second operation bias resistor that is provided between the emitter terminal of the second output transistor and the base terminal of the first clamp transistor.
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Abstract
There is provided a buffer circuit that outputs a signal according to an input signal. The buffer circuit includes a first receiving transistor that receives the input signal through its base terminal, a first clamp transistor having polarity same as that of the first receiving transistor, of which an emitter terminal and a collector terminal are connected to corresponding terminals of the first receiving transistor and which receives a first clamp voltage restricting a signal level output from the buffer circuit through its base terminal, and a first current defining section that is commonly provided for the first receiving transistor and the first clamp transistor and defines a total amount of emitter currents flowing into the first receiving transistor and the first clamp transistor. The buffer circuit outputs an output signal according to an emitter voltage of the first receiving transistor.
14 Citations
28 Claims
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1. A buffer circuit that outputs a signal according to an input signal, comprising:
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a first receiving transistor that receives the input signal through its base terminal; a first clamp transistor having polarity the same as that of the first receiving transistor, of which an emitter terminal and a collector terminal are connected to corresponding terminals of the first receiving transistor and which receives a first clamp voltage restricting a signal level output from the buffer circuit through its base terminal; and a first current defining section that is commonly provided for the first receiving transistor and the first clamp transistor and defines a total amount of emitter currents flowing into the first receiving transistor and the first clamp transistor, wherein the buffer circuit outputs an output signal according to an emitter voltage of the first receiving transistor, the buffer circuit further comprising; a first output transistor having polarity different from that of the first receiving transistor and the first clamp transistor, of which a base terminal is connected to the emitter terminal of the first transistor and the emitter terminal of the first clamp transistor and which outputs the output signal according to a receiving signal through its base terminal, wherein the first receiving transistor outputs, when a signal level of the input signal is within a range defined by the first clamp voltage, a signal having a signal level according to the input signal, the first clamp transistor outputs, when the signal level of the input signal is out of a range defined by the first clamp voltage, a signal having a signal level according to the first clamp voltage, the first receiving transistor generates a signal having a signal level obtained by adding or subtracting a voltage between the base and the emitter to or from the signal level of the input signal through its emitter terminal, the first clamp transistor generates a signal having a signal level obtained by adding or subtracting a voltage between the base and the emitter to or from the first clamp voltage through its emitter terminal, and the first output transistor outputs an output signal having a signal level obtained by subtracting or adding a voltage between the base and the emitter from or to a signal level of the signal received through its base terminal, the buffer circuit further comprising; a second receiving transistor having polarity different from that of the first receiving transistor, which is provided in parallel with the first receiving transistor and receives the input signal through its base terminal; a second clamp transistor having polarity the same as that of the second receiving transistor, of which an emitter terminal and a collector terminal are connected to corresponding terminals of the second receiving transistor and which receives a second clamp voltage smaller than the first clamp voltage through its base terminal; a second current defining section that is commonly provided for the second receiving transistor and the second clamp transistor and defines a total amount of emitter currents flowing into the second receiving transistor and the second clamp transistor; a second output transistor having polarity different from that of the second receiving transistor and the second clamp transistor, of which a base terminal is connected to an emitter terminal of the second transistor and an emitter terminal of the second clamp transistor and which outputs the output signal according to a receiving signal through its base terminal; a first operation bias resistor that is provided between the emitter terminal of the first output transistor and the base terminal of the second clamp transistor; and a second operation bias resistor that is provided between the emitter terminal of the second output transistor and the base terminal of the first clamp transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A buffer circuit that outputs a signal according to an input signal, comprising:
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a first receiving transistor that receives the input signal through its base terminal; a first clamp transistor having polarity the same as that of the first receiving transistor, of which an emitter terminal and a collector terminal are connected to corresponding terminals of the first receiving transistor and which receives a first clamp voltage restricting a signal level output from the buffer circuit through its base terminal; and a first current defining section that is commonly provided for the first receiving transistor and the first clamp transistor and defines a total amount of emitter currents flowing into the first receiving transistor and the first clamp transistor, wherein the buffer circuit outputs an output signal according to an emitter voltage of the first receiving transistor, the buffer circuit further comprising; a first output transistor having polarity different from that of the first receiving transistor and the first clamp transistor, of which a base terminal is connected to the emitter terminal of the first transistor and the emitter terminal of the first clamp transistor and which outputs the output signal according to a receiving signal through its base terminal, wherein the first receiving transistor outputs, when a signal level of the input signal is within a range defined by the first clamp voltage, a signal having a signal level according to the input signal, the first clamp transistor outputs, when the signal level of the input signal is out of a range defined by the first clamp voltage, a signal having a signal level according to the first clamp voltage, the first receiving transistor generates a signal having a signal level obtained by adding or subtracting a voltage between the base and the emitter to or from the signal level of the input signal through its emitter terminal, the first clamp transistor generates a signal having a signal level obtained by adding or subtracting a voltage between the base and the emitter to or from the first clamp voltage through its emitter terminal, and the first output transistor outputs an output signal having a signal level obtained by subtracting or adding a voltage between the base and the emitter from or to a signal level of the signal received through its base terminal, the buffer circuit further comprising; a second receiving transistor having polarity different from that of the first receiving transistor, which is provided in parallel with the first receiving transistor and receives the input signal through its base terminal; a second clamp transistor having polarity the same as that of the second receiving transistor, of which an emitter terminal and a collector terminal are connected to corresponding terminals of the second receiving transistor and which receives a second clamp voltage smaller than the first clamp voltage through its base terminal; a second current defining section that is commonly provided for the second receiving transistor and the second clamp transistor and defines a total amount of emitter currents flowing into the second receiving transistor and the second clamp transistor; a second output transistor having polarity different from that of the second receiving transistor and the second clamp transistor, of which a base terminal is connected to an emitter terminal of the second transistor and an emitter terminal of the second clamp transistor and which outputs the output signal according to a receiving signal through its base terminal; and a common operation bias resistor that connects the emitter terminal of the first output transistor and the emitter terminal of the second output transistor to an electric potential between the first clamp voltage and the second clamp voltage. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A buffer circuit that outputs a signal according to an input signal, comprising:
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a first receiving transistor that receives the input signal through its base terminal; a first clamp transistor having polarity the same as that of the first receiving transistor, of which an emitter terminal and a collector terminal are connected to corresponding terminals of the first receiving transistor and which receives a first clamp voltage restricting a signal level output from the buffer circuit through its base terminal; and a first current defining section that is commonly provided for the first receiving transistor and the first clamp transistor and defines a total amount of emitter currents flowing into the first receiving transistor and the first clamp transistor, wherein the buffer circuit outputs an output signal according to an emitter voltage of the first receiving transistor, the buffer circuit further comprising; a first output transistor having polarity different from that of the first receiving transistor and the first clamp transistor, of which a base terminal is connected to the emitter terminal of the first transistor and the emitter terminal of the first clamp transistor and which outputs the output signal according to a receiving signal through its base terminal; and a first diode that is provided between the base terminal of the first receiving transistor and the base terminal of the first clamp transistor. - View Dependent Claims (24, 25, 26, 27, 28)
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Specification
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Current AssigneeAdvantest Corporation
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Original AssigneeAdvantest Corporation
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InventorsKimura, Hiroki
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Primary Examiner(s)Hollington; Jermele M
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Application NumberUS11/829,939Publication NumberTime in Patent Office912 DaysField of SearchNoneUS Class Current324/123.00RCPC Class CodesG01R 1/30 Structural combination of e...G01R 19/2506 Arrangements for conditioni...H03F 2203/45552 the IC comprising clamping ...H03F 2203/5021 the source follower has a c...H03F 3/4508 using bipolar transistors a...H03F 3/50 Amplifiers in which input i...H03G 11/002 without controlling loop H0...H03K 19/01812 with at least one different...
